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* alumacc skeletonClifford Wolf2014-09-142-0/+64
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* Added "$fa" cell typeClifford Wolf2014-09-081-6/+16
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* Trim msb/lsb zero bits from full adder in maccmapClifford Wolf2014-09-081-5/+27
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* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-071-19/+53
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* Added "maccmap" commandClifford Wolf2014-09-072-0/+319
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* Removed $bu0 cell typeClifford Wolf2014-09-041-12/+1
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* Added "techmap -autoproc"Clifford Wolf2014-09-011-2/+18
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* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-271-0/+5
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* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-231-2/+1
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-235-32/+41
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* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-231-4/+5
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* Renamed toposort.h to utils.hClifford Wolf2014-08-171-1/+1
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* Bugfix in iopadmapClifford Wolf2014-08-151-1/+3
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-152-5/+5
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* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-3/+3
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* document "techmap -map %<design-name>"Clifford Wolf2014-08-151-0/+3
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* Added module->portsClifford Wolf2014-08-141-2/+2
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* Implemented recursive techmapClifford Wolf2014-08-031-16/+62
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* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-021-5/+40
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* Bugfix in "techmap -extern"Clifford Wolf2014-08-021-0/+1
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-022-3/+3
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* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-022-4/+6
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-024-38/+38
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* Replaced sha1 implementationClifford Wolf2014-08-011-6/+1
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-315-98/+98
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-1/+1
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-312-2/+2
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* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-313-6/+6
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* Added "techmap -assert"Clifford Wolf2014-07-311-13/+42
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* Added techmap CONSTMAP featureClifford Wolf2014-07-301-10/+119
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* Added "techmap -map %{design-name}"Clifford Wolf2014-07-292-10/+19
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* Using log_assert() instead of assert()Clifford Wolf2014-07-283-7/+4
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* Added techmap -externClifford Wolf2014-07-271-16/+64
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* Added topological sorting to techmapClifford Wolf2014-07-271-20/+52
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* Using new obj iterator API in a few placesClifford Wolf2014-07-272-21/+19
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-276-21/+21
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-274-10/+10
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-273-12/+12
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* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-263-17/+7
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* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-261-2/+2
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* Manual fixes for new cell connections APIClifford Wolf2014-07-266-16/+18
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-266-128/+128
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-266-128/+128
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* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-261-8/+4
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-256-122/+59
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* Added "make SMALL=1"Clifford Wolf2014-07-241-1/+4
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* Added "make PRETTY=1"Clifford Wolf2014-07-241-6/+6
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* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-232-131/+69
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-233-25/+24
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-232-3/+3
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