Manual fixes for new cell connections API

6 files changed, 18 insertions, 16 deletions

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 1dce39f69..eabc56bd2 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -418,7 +418,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 			} else
 			if (port.second != 0)
 				log_abort();
-			new_cell->connections()["\\" + port.first] = sig;
+			new_cell->set("\\" + port.first, sig);
 		}
 
 		stats[stringf("  mapped %%d %s cells to %s cells.\n", cell_type.c_str(), new_cell->type.c_str())]++;
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 0d8f6ab0d..6439302cd 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -305,7 +305,7 @@ namespace
 			if (wire->port_id > 0) {
 				for (int i = 0; i < wire->width; i++)
 					sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
-				cell->connections()[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
+				cell->set(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
 			}
 		}
 
@@ -325,7 +325,9 @@ namespace
 					for (int i = 0; i < sig.size(); i++)
 					for (auto &port : sig2port.find(sig[i])) {
 						RTLIL::SigSpec bitsig = haystack_cell->connections().at(mapping.portMapping[conn.first]).extract(i, 1);
-						cell->connections().at(port.first).replace(port.second, bitsig);
+						RTLIL::SigSpec new_sig = cell->get(port.first);
+						new_sig.replace(port.second, bitsig);
+						cell->set(port.first, new_sig);
 					}
 				}
 			}
@@ -744,7 +746,7 @@ struct ExtractPass : public Pass {
 						for (auto &chunk : chunks)
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires.at(chunk.wire->name);
-						newCell->connections()[conn.first] = chunks;
+						newCell->set(conn.first, chunks);
 					}
 				}
 			}
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index 2e5dd7dca..309777876 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_hi == RTLIL::State::Sm) {
 				last_hi = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
-				cell->connections()[RTLIL::escape_id(hicell_portname)] = last_hi;
+				cell->set(RTLIL::escape_id(hicell_portname), last_hi);
 			}
 			bit = last_hi;
 		}
@@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 			if (!singleton_mode || last_lo == RTLIL::State::Sm) {
 				last_lo = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
-				cell->connections()[RTLIL::escape_id(locell_portname)] = last_lo;
+				cell->set(RTLIL::escape_id(locell_portname), last_lo);
 			}
 			bit = last_lo;
 		}
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 199fd6029..114d28e25 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -177,9 +177,9 @@ struct IopadmapPass : public Pass {
 					for (int i = 0; i < wire->width; i++)
 					{
 						RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-						cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
+						cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
 						if (!portname2.empty())
-							cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
+							cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
 						if (!widthparam.empty())
 							cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
 						if (!nameparam.empty())
@@ -190,9 +190,9 @@ struct IopadmapPass : public Pass {
 				else
 				{
 					RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
-					cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
+					cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
 					if (!portname2.empty())
-						cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
+						cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
 					if (!widthparam.empty())
 						cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
 					if (!nameparam.empty())
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index f8851400f..355c07c84 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -128,7 +128,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 	if (cell->type == "$reduce_bool") gate_type = "$_OR_";
 	log_assert(!gate_type.empty());
 
-	RTLIL::SigSpec *last_output = NULL;
+	RTLIL::Cell *last_output_cell = NULL;
 
 	while (sig_a.size() > 1)
 	{
@@ -145,7 +145,7 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 			gate->set("\\A", sig_a[i]);
 			gate->set("\\B", sig_a[i+1]);
 			gate->set("\\Y", sig_t[i/2]);
-			last_output = &gate->get("\\Y");
+			last_output_cell = gate;
 		}
 
 		sig_a = sig_t;
@@ -156,14 +156,14 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
 		RTLIL::Cell *gate = module->addCell(NEW_ID, "$_INV_");
 		gate->set("\\A", sig_a);
 		gate->set("\\Y", sig_t);
-		last_output = &gate->get("\\Y");
+		last_output_cell = gate;
 		sig_a = sig_t;
 	}
 
-	if (last_output == NULL) {
+	if (last_output_cell == NULL) {
 		module->connect(RTLIL::SigSig(sig_y, sig_a));
 	} else {
-		*last_output = sig_y;
+		last_output_cell->set("\\Y", sig_y);
 	}
 }
 
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 4c8f92505..9dcd6a45b 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -195,7 +195,7 @@ struct TechmapWorker
 			if (!flatten_mode && c->type.substr(0, 2) == "\\$")
 				c->type = c->type.substr(1);
 
-			for (auto &it2 : c->connections()) {
+			for (auto &it2 : c->connections_) {
 				apply_prefix(cell->name, it2.second, module);
 				port_signal_map.apply(it2.second);
 			}