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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-14 16:13:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-14 16:22:52 +0200 |
| commit | 1bf7a18fec76cf46a5b8710a75371e23b68d147d (patch) | |
| tree | ea445edda6c4bc0fa670effce4ef1b0eaf906258 /passes/techmap | |
| parent | 746aac540b815099c6a63077010555369d7fdd5a (diff) | |
| download | yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.tar.gz yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.tar.bz2 yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.zip | |
Added module->ports
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/extract.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 985d51e50..ebf4d77fc 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -726,14 +726,14 @@ struct ExtractPass : public Pass { newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits); map->add(newMod); - int portCounter = 1; for (auto wire : wires) { RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width); - newWire->port_id = portCounter++; newWire->port_input = true; newWire->port_output = true; } + newMod->fixup_ports(); + for (auto cell : cells) { RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type); newCell->parameters = cell->parameters; |