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* Fix crash in flowmapDag Lem2022-09-201-1/+2
| | | | | | | | | | | | In 2fcc1ee72e, the following is apparantly added in order to mark any number of undefined LUT inputs: lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size())); However this can only be done if the number of input nodes is less than minlut. This fixes #3317
* Fix tmpdir naming when passing -nocleanup option to abc(9) on systems where ↵N. Engelhardt2022-09-132-6/+12
| | | | base_tmpdir isn't /tmp/
* Merge pull request #3458 from QuantamHD/abc_fasterN. Engelhardt2022-08-311-6/+6
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| * Improves ABC command runtime by 10-100xEthan Mahintorabi2022-08-241-6/+6
| | | | | | | | | | | | | | | | After speaking with the author of ABC he let me know that ifraig is a very old command, and that &get; &fraig -x; &put is over 100x faster than ifraig with improved PPA results. After making the change I confirmed that this is in fact a major speed up. On our internal designs in O(millions) of standard cells we saw multi hour reductions in runtime. Also included is an improvement to the dress command. Using AIG based transformations removes the spec it SATs against. Proving the input blif will make sure that no matter what commands are run the dress command can still do its job. I noticed a regression against some LUT mapping jobs that prompted me to fix this.
* | Fitting help messages to 80 character widthKrystalDelusion2022-08-249-63/+57
|/ | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* support file locations containing spacesMiodrag Milanovic2022-08-082-8/+8
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* Fix external ABC build after commit 0ca0932b5.Catherine2022-07-072-4/+8
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* iopadmap: Fix z assignment removal.Marcelina Kościelnicka2022-06-071-7/+21
| | | | Fixes #3360.
* Observe $TMPDIR variable when creating tmp filesMohamed A. Bamakhrama2022-05-272-2/+2
| | | | | | | | | POSIX defines $TMPDIR as containing the pathname of the directory where programs can create temporary files. On most systems, this variable points to "/tmp". However, on some systems it can point to a different location. Without respecting this variable, yosys fails to run on such systems. Signed-off-by: Mohamed A. Bamakhrama <mohamed@alumni.tum.de>
* abc9_ops: Don't leave unused derived modules lying aroundgatecat2022-05-231-0/+9
| | | | | | | These later become accidentally used for techmap replacements for blackboxes that we don't actually want. Signed-off-by: gatecat <gatecat@ds0.me>
* abc: Use dict/pool instead of std::map/std::setMarcelina Kościelnicka2022-05-041-14/+14
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* tribuf: `-formal` option: convert all to logic and detect conflictsJannis Harder2022-04-121-3/+46
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* abc: Add support for FFs with reset in -dffMarcelina Kościelnicka2022-04-071-90/+229
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* Merge pull request #3194 from Ravenslofty/abc9-flow3mfsLofty2022-03-281-1/+7
|\ | | | | abc9: add flow3mfs script
| * abc9: add flow3mfs scriptLofty2022-02-101-1/+7
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* | abc9_ops: Also derive blackboxes with timing infogatecat2022-03-241-5/+10
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | abc: Fix {I} and {P} substitutionAnton Blanchard2022-02-231-2/+2
| | | | | | | | We were searching for {D} after the first match of {I} or {P}.
* | Correct a typo in the manualYRabbit2022-02-021-1/+1
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-284-1/+183
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* sta: very crude static timing analysis passLofty2021-11-251-30/+28
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Merge pull request #3077 from YosysHQ/claire/genlibClaire Xen2021-11-101-21/+40
|\ | | | | Add genlib support to ABC command
| * Spelling fix in abc.ccClaire Xen2021-11-101-1/+1
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| * Add genlib support to ABC commandClaire Xenia Wolf2021-11-101-21/+40
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | iopadmap: Fix ebmarassing typoMarcelina Kościelnicka2021-11-101-1/+1
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* | iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-091-7/+22
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* flatten: Keep sigmap around between flatten_cell invocations.Marcelina Kościelnicka2021-11-021-3/+4
| | | | Fixes #3064.
* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-271-973/+889
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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-1/+3
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-211-4/+6
| | | | Also fixes some completely broken code in extract_reduce.
* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-211-63/+34
| | | | Fixes #3047.
* dfflegalize: remove redundant check for initialized dlatchPaul Annesley2021-10-171-4/+0
| | | | | | This if condition is repeated verbatim, and I can't imagine a legitimate way the inputs could change in between. I imagine it's a copy/paste mistake.
* FfData: some refactoring.Marcelina Kościelnicka2021-10-073-50/+15
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-1/+3
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* zinit: Refactor to use FfData.Marcelina Kościelnicka2021-10-021-101/+38
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* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-2/+2
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-022-287/+20
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* abc9: make re-entrant (#2993)Eddie Hung2021-09-092-9/+9
| | | | | | | | | * Add testcase * Cleanup some state at end of abc9 * Re-assign abc9_box_id from scratch * Suppress delete unless prep_bypass did something
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-1/+1
| | | | | * Add testcase * holes module to instantiate cells with NEW_ID
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-6/+22
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-0/+1
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* Fix deadname SVN linksClaire Xenia Wolf2021-06-092-3/+3
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0833-33/+33
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-223-22/+5
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* flatten: rewrite memid in memwr actions.whitequark2021-04-091-0/+3
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* abc9: uniquify blackboxes like whiteboxes (#2695)Eddie Hung2021-03-291-10/+6
| | | | | | | | | * abc9_ops: uniquify blackboxes too * abc9_ops: update comment * abc9_ops: allow bypass for param-less blackboxes * Add tests
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-292-28/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* Replace assert in abc9_ops with more useful error messageDan Ravensloft2021-03-071-1/+9
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* Fixes command line for abc pass in -fast -sop modeRobert Baruch2021-02-161-1/+1
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* Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-041-23/+22
|\ | | | | verilog: significant block scoping improvements
| * verilog: significant block scoping improvementsZachary Snow2021-01-311-23/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 02:42:44 +0000