Fitting help messages to 80 character width

Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.

9 files changed, 57 insertions, 63 deletions

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 656c36b84..4039336dd 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1532,7 +1532,8 @@ struct AbcPass : public Pass {
 		log("           NMUX, AOI3, OAI3, AOI4, OAI4.\n");
 		log("        (The NOT gate is always added to this list automatically.)\n");
 		log("\n");
-		log("        The following aliases can be used to reference common sets of gate types:\n");
+		log("        The following aliases can be used to reference common sets of gate\n");
+		log("        types:\n");
 		log("          simple: AND OR XOR MUX\n");
 		log("          cmos2:  NAND NOR\n");
 		log("          cmos3:  NAND NOR AOI3 OAI3\n");
@@ -1576,8 +1577,8 @@ struct AbcPass : public Pass {
 		log("\n");
 		log("    -dress\n");
 		log("        run the 'dress' command after all other ABC commands. This aims to\n");
-		log("        preserve naming by an equivalence check between the original and post-ABC\n");
-		log("        netlists (experimental).\n");
+		log("        preserve naming by an equivalence check between the original and\n");
+		log("        post-ABC netlists (experimental).\n");
 		log("\n");
 		log("When no target cell library is specified the Yosys standard cell library is\n");
 		log("loaded into ABC before the ABC script is executed.\n");
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 79c994b11..88fac67e8 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -93,8 +93,8 @@ struct Abc9Pass : public ScriptPass
 		log("\n");
 		log("    abc9 [options] [selection]\n");
 		log("\n");
-		log("This script pass performs a sequence of commands to facilitate the use of the ABC\n");
-		log("tool [1] for technology mapping of the current design to a target FPGA\n");
+		log("This script pass performs a sequence of commands to facilitate the use of the\n");
+		log("ABC tool [1] for technology mapping of the current design to a target FPGA\n");
 		log("architecture. Only fully-selected modules are supported.\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc
index 2f46c89f4..1d9bb4332 100644
--- a/passes/techmap/abc9_exe.cc
+++ b/passes/techmap/abc9_exe.cc
@@ -303,8 +303,8 @@ struct Abc9ExePass : public Pass {
 		log("\n");
 		log(" \n");
 		log("This pass uses the ABC tool [1] for technology mapping of the top module\n");
-		log("(according to the (* top *) attribute or if only one module is currently selected)\n");
-		log("to a target FPGA architecture.\n");
+		log("(according to the (* top *) attribute or if only one module is currently\n");
+		log("selected) to a target FPGA architecture.\n");
 		log("\n");
 		log("    -exe <command>\n");
 #ifdef ABCEXTERNAL
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index acafb0b65..9766e81cb 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -1572,14 +1572,14 @@ struct Abc9OpsPass : public Pass {
 		log("the `abc9' script pass. Only fully-selected modules are supported.\n");
 		log("\n");
 		log("    -check\n");
-		log("        check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
-		log("        (* abc9_carry *) is only given for one input/output port, etc.\n");
+		log("        check that the design is valid, e.g. (* abc9_box_id *) values are\n");
+		log("        unique, (* abc9_carry *) is only given for one input/output port, etc.\n");
 		log("\n");
 		log("    -prep_hier\n");
 		log("        derive all used (* abc9_box *) or (* abc9_flop *) (if -dff option)\n");
 		log("        whitebox modules. with (* abc9_flop *) modules, only those containing\n");
-		log("        $dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC limitation\n");
-		log("        -- will be derived.\n");
+		log("        $dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC\n");
+		log("        limitation -- will be derived.\n");
 		log("\n");
 		log("    -prep_bypass\n");
 		log("        create techmap rules in the '$abc9_map' and '$abc9_unmap' designs for\n");
@@ -1597,33 +1597,35 @@ struct Abc9OpsPass : public Pass {
 		log("    -prep_dff_submod\n");
 		log("        within (* abc9_flop *) modules, rewrite all edge-sensitive path\n");
 		log("        declarations and $setup() timing checks ($specify3 and $specrule cells)\n");
-		log("        that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port to\n");
-		log("        the DFF's 'D' port. this is to prepare such specify cells to be moved\n");
+		log("        that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port\n");
+		log("        to the DFF's 'D' port. this is to prepare such specify cells to be moved\n");
 		log("        into the flop box.\n");
 		log("\n");
 		log("    -prep_dff_unmap\n");
-		log("        populate the '$abc9_unmap' design with techmap rules for mapping *_$abc9_flop\n");
-		log("        cells back into their derived cell types (where the rules created by\n");
-		log("        -prep_hier will then map back to the original cell with parameters).\n");
+		log("        populate the '$abc9_unmap' design with techmap rules for mapping\n");
+		log("        *_$abc9_flop cells back into their derived cell types (where the rules\n");
+		log("        created by -prep_hier will then map back to the original cell with\n");
+		log("        parameters).\n");
 		log("\n");
 		log("    -prep_delays\n");
 		log("        insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
 		log("        certain required times.\n");
 		log("\n");
 		log("    -break_scc\n");
-		log("        for an arbitrarily chosen cell in each unique SCC of each selected module\n");
-		log("        (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt all wires\n");
-		log("        driven by this cell's outputs with a temporary $__ABC9_SCC_BREAKER cell\n");
-		log("        to break the SCC.\n");
+		log("        for an arbitrarily chosen cell in each unique SCC of each selected\n");
+		log("        module (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt\n");
+		log("        all wires driven by this cell's outputs with a temporary\n");
+		log("        $__ABC9_SCC_BREAKER cell to break the SCC.\n");
 		log("\n");
 		log("    -prep_xaiger\n");
 		log("        prepare the design for XAIGER output. this includes computing the\n");
-		log("        topological ordering of ABC9 boxes, as well as preparing the '$abc9_holes'\n");
-		log("        design that contains the logic behaviour of ABC9 whiteboxes.\n");
+		log("        topological ordering of ABC9 boxes, as well as preparing the \n");
+		log("        '$abc9_holes' design that contains the logic behaviour of ABC9\n");
+		log("        whiteboxes.\n");
 		log("\n");
 		log("    -dff\n");
-		log("        consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
-		log("        during -prep_{delays,xaiger,box}.\n");
+		log("        consider flop cells (those instantiating modules marked with\n");
+		log("        (* abc9_flop *)) during -prep_{delays,xaiger,box}.\n");
 		log("\n");
 		log("    -prep_lut <maxlut>\n");
 		log("        pre-compute the lut library by analysing all modules marked with\n");
@@ -1641,8 +1643,8 @@ struct Abc9OpsPass : public Pass {
 		log("\n");
 		log("    -reintegrate\n");
 		log("        for each selected module, re-intergrate the module '<module-name>$abc9'\n");
-		log("        by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
-		log("        inputs and outputs.\n");
+		log("        by first recovering ABC9 boxes, and then stitching in the remaining\n");
+		log("        primary inputs and outputs.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc
index 1d99caa3a..c6c3a58c5 100644
--- a/passes/techmap/dfflegalize.cc
+++ b/passes/techmap/dfflegalize.cc
@@ -118,34 +118,24 @@ struct DffLegalizePass : public Pass {
 		log("- $_DLATCH_[NP][NP][01]_\n");
 		log("- $_DLATCHSR_[NP][NP][NP]_\n");
 		log("\n");
-		log("The following transformations are performed by this pass:");
-		log("\n");
-		log("- upconversion from a less capable cell to a more capable cell, if the less");
-		log("  capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)");
-		log("\n");
-		log("- unmapping FFs with clock enable (due to unsupported cell type or -mince)");
-		log("\n");
-		log("- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)");
-		log("\n");
-		log("- adding inverters on the control pins (due to unsupported polarity)");
+		log("The following transformations are performed by this pass:\n");
 		log("\n");
+		log("- upconversion from a less capable cell to a more capable cell, if the less\n");
+		log("  capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)\n");
+		log("- unmapping FFs with clock enable (due to unsupported cell type or -mince)\n");
+		log("- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)\n");
+		log("- adding inverters on the control pins (due to unsupported polarity)\n");
 		log("- adding inverters on the D and Q pins and inverting the init/reset values\n");
-		log("  (due to unsupported init or reset value)");
-		log("\n");
-		log("- converting sr into adlatch (by tying D to 1 and using E as set input)");
-		log("\n");
-		log("- emulating unsupported dffsr cell by adff + adff + sr + mux");
-		log("\n");
-		log("- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux");
-		log("\n");
+		log("  (due to unsupported init or reset value)\n");
+		log("- converting sr into adlatch (by tying D to 1 and using E as set input)\n");
+		log("- emulating unsupported dffsr cell by adff + adff + sr + mux\n");
+		log("- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux\n");
 		log("- emulating adff when the (reset, init) value combination is unsupported by\n");
-		log("  dff + adff + dlatch + mux");
-		log("\n");
+		log("  dff + adff + dlatch + mux\n");
 		log("- emulating adlatch when the (reset, init) value combination is unsupported by\n");
-		log("- dlatch + adlatch + dlatch + mux");
-		log("\n");
-		log("If the pass is unable to realize a given cell type (eg. adff when only plain dff");
-		log("is available), an error is raised.");
+		log("- dlatch + adlatch + dlatch + mux\n");
+		log("If the pass is unable to realize a given cell type (eg. adff when only plain dff\n");
+		log("is available), an error is raised.\n");
 	}
 
 	// Table of all supported cell types.
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 252baae9a..12c3a95de 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -431,7 +431,7 @@ struct DfflibmapPass : public Pass {
 		log("cells, leaving remaining internal cells untouched.\n");
 		log("\n");
 		log("When called with -info, this command will only print the target cell\n");
-		log("list, along with their associated internal cell types, and the arguments");
+		log("list, along with their associated internal cell types, and the arguments\n");
 		log("that would be passed to the dfflegalize pass.  The design will not be\n");
 		log("changed.\n");
 		log("\n");
diff --git a/passes/techmap/dffunmap.cc b/passes/techmap/dffunmap.cc
index 7312015f1..8703bf1a0 100644
--- a/passes/techmap/dffunmap.cc
+++ b/passes/techmap/dffunmap.cc
@@ -33,8 +33,8 @@ struct DffunmapPass : public Pass {
 		log("    dffunmap [options] [selection]\n");
 		log("\n");
 		log("This pass transforms FF types with clock enable and/or synchronous reset into\n");
-		log("their base type (with neither clock enable nor sync reset) by emulating the clock\n");
-		log("enable and synchronous reset with multiplexers on the cell input.\n");
+		log("their base type (with neither clock enable nor sync reset) by emulating the\n");
+		log("clock enable and synchronous reset with multiplexers on the cell input.\n");
 		log("\n");
 		log("    -ce-only\n");
 		log("        unmap only clock enables, leave synchronous resets alone.\n");
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 7d8dba439..f75b82919 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -476,7 +476,8 @@ struct SimplemapPass : public Pass {
 		log("  $not, $pos, $and, $or, $xor, $xnor\n");
 		log("  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
 		log("  $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
-		log("  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
+		log("  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff,\n");
+		log("  $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 5cd78fe28..144f596c8 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -1026,8 +1026,8 @@ struct TechmapPass : public Pass {
 		log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
 		log("match cells with a type that match the text value of this attribute. Otherwise\n");
 		log("the module name will be used to match the cell.  Multiple space-separated cell\n");
-		log("types can be listed, and wildcards using [] will be expanded (ie. \"$_DFF_[PN]_\"\n");
-		log("is the same as \"$_DFF_P_ $_DFF_N_\").\n");
+		log("types can be listed, and wildcards using [] will be expanded (ie.\n");
+		log("\"$_DFF_[PN]_\" is the same as \"$_DFF_P_ $_DFF_N_\").\n");
 		log("\n");
 		log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
 		log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
@@ -1083,11 +1083,11 @@ struct TechmapPass : public Pass {
 		log("        It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
 		log("\n");
 		log("    _TECHMAP_REMOVEINIT_<port-name>_\n");
-		log("        When this wire is set to a constant value, the init attribute of the wire(s)\n");
-		log("        connected to this port will be consumed.  This wire must have the same\n");
-		log("        width as the given port, and for every bit that is set to 1 in the value,\n");
-		log("        the corresponding init attribute bit will be changed to 1'bx.  If all\n");
-		log("        bits of an init attribute are left as x, it will be removed.\n");
+		log("        When this wire is set to a constant value, the init attribute of the\n");
+		log("        wire(s) connected to this port will be consumed.  This wire must have\n");
+		log("        the same width as the given port, and for every bit that is set to 1 in\n");
+		log("        the value, the corresponding init attribute bit will be changed to 1'bx.\n");
+		log("        If all bits of an init attribute are left as x, it will be removed.\n");
 		log("\n");
 		log("In addition to this special wires, techmap also supports special parameters in\n");
 		log("modules in the map file:\n");
@@ -1108,8 +1108,8 @@ struct TechmapPass : public Pass {
 		log("\n");
 		log("    _TECHMAP_WIREINIT_<port-name>_\n");
 		log("        When a parameter with this name exists, it will be set to the initial\n");
-		log("        value of the wire(s) connected to the given port, as specified by the init\n");
-		log("        attribute. If the attribute doesn't exist, x will be filled for the\n");
+		log("        value of the wire(s) connected to the given port, as specified by the\n");
+		log("        init attribute. If the attribute doesn't exist, x will be filled for the\n");
 		log("        missing bits.  To remove the init attribute bits used, use the\n");
 		log("        _TECHMAP_REMOVEINIT_*_ wires.\n");
 		log("\n");