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* Fix debugEddie Hung2019-11-251-3/+3
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-251-0/+41
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| * clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-0/+41
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* | abc9 to contain time callEddie Hung2019-11-251-1/+1
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* | abc9 to no longer to clock partitioning, operate on whole modules onlyEddie Hung2019-11-251-139/+32
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* | Conditioning abc9 on POs not accurate due to cellsEddie Hung2019-11-231-15/+6
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* | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-222-270/+0
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| * | Move clkpart into passes/hierarchyEddie Hung2019-11-222-270/+0
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* | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-221-8/+9
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| * | Only action if there is more than one clock domainEddie Hung2019-11-221-7/+8
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| * | Replace TODOEddie Hung2019-11-221-1/+1
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* | | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-222-1/+2
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| * | BracketsEddie Hung2019-11-221-1/+1
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| * | Entry in Makefile.incEddie Hung2019-11-221-0/+1
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* | | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-221-0/+268
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| * | New 'clkpart' to {,un}partition design according to clock/enableEddie Hung2019-11-221-0/+268
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* | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_Eddie Hung2019-11-211-1/+1
| | | | | | | | Since they should be captured downwards from the owning flop
* | endomain -> ctrldomainEddie Hung2019-11-201-3/+3
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-192-6/+11
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| * Fix #1496.Marcin Kościelnicki2019-11-181-4/+8
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| * flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
| | | | | | | | Fixes #1475.
| * flowmap: don't break if that creates a k+2 (and larger) LUT either.whitequark2019-11-111-1/+1
| | | | | | | | Fixes #1405.
| * Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-041-3/+12
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* | | Use "abc9_period" attribute for delay targetEddie Hung2019-10-071-3/+24
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* | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-30/+6
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* | | Fix from mergeEddie Hung2019-10-041-1/+1
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-041-2/+12
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| * | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`Eddie Hung2019-10-041-3/+13
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* | | Fix merge issuesEddie Hung2019-10-042-10/+2
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* | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-68/+67
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| * | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-65/+65
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-10-031-0/+14
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| * Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-6/+40
| |\ | | | | | | Add -select option to aigmap
| | * Add -select option to aigmapEddie Hung2019-09-301-6/+40
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| * | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
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| * | techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* | No need to punch ports at allEddie Hung2019-09-301-13/+0
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* | Resolve FIXME on calling proc just onceEddie Hung2019-09-301-2/+2
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* | Remove need for $currQ port connectionEddie Hung2019-09-301-0/+8
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* | Add commentEddie Hung2019-09-301-0/+1
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* | scc call on active module module only, plus cleanupEddie Hung2019-09-301-21/+16
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-301-1/+1
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| * Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-301-1/+1
| |\ | | | | | | Open aig frontend as binary file
| | * Open aig frontend as binary fileMiodrag Milanovic2019-09-291-1/+1
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-3/+16
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| * | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-291-3/+16
| |\ \ | | |/ | |/| DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| | * "abc_padding" attr for blackbox outputs that were padded, remove them laterEddie Hung2019-09-231-3/+16
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* | | Fix "scc" call inside abc9 to consider all wiresEddie Hung2019-09-291-1/+1
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* | | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-281-78/+65
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* | | Split ABC9 based on clocking only, add "abc_mergeability" attr for enEddie Hung2019-09-271-88/+28
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