| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fix debug | Eddie Hung | 2019-11-25 | 1 | -3/+3 |
| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 1 | -0/+41 |
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| | * | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -0/+41 |
| * | | abc9 to contain time call | Eddie Hung | 2019-11-25 | 1 | -1/+1 |
| * | | abc9 to no longer to clock partitioning, operate on whole modules only | Eddie Hung | 2019-11-25 | 1 | -139/+32 |
| * | | Conditioning abc9 on POs not accurate due to cells | Eddie Hung | 2019-11-23 | 1 | -15/+6 |
| * | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -270/+0 |
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| | * | | Move clkpart into passes/hierarchy | Eddie Hung | 2019-11-22 | 2 | -270/+0 |
| * | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -8/+9 |
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| | * | | Only action if there is more than one clock domain | Eddie Hung | 2019-11-22 | 1 | -7/+8 |
| | * | | Replace TODO | Eddie Hung | 2019-11-22 | 1 | -1/+1 |
| * | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -1/+2 |
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| | * | | Brackets | Eddie Hung | 2019-11-22 | 1 | -1/+1 |
| | * | | Entry in Makefile.inc | Eddie Hung | 2019-11-22 | 1 | -0/+1 |
| * | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+268 |
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| | * | | New 'clkpart' to {,un}partition design according to clock/enable | Eddie Hung | 2019-11-22 | 1 | -0/+268 |
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| * | | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ | Eddie Hung | 2019-11-21 | 1 | -1/+1 |
| * | | endomain -> ctrldomain | Eddie Hung | 2019-11-20 | 1 | -3/+3 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 2 | -6/+11 |
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| | * | Fix #1496. | Marcin Kościelnicki | 2019-11-18 | 1 | -4/+8 |
| | * | flowmap: when doing mincut, ensure source is always in X, not X̅. | whitequark | 2019-11-12 | 1 | -1/+2 |
| | * | flowmap: don't break if that creates a k+2 (and larger) LUT either. | whitequark | 2019-11-11 | 1 | -1/+1 |
| | * | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+12 |
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| * | | | Use "abc9_period" attribute for delay target | Eddie Hung | 2019-10-07 | 1 | -3/+24 |
| * | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 1 | -30/+6 |
| * | | | Fix from merge | Eddie Hung | 2019-10-04 | 1 | -1/+1 |
| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -2/+12 |
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| | * | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -3/+13 |
| * | | | Fix merge issues | Eddie Hung | 2019-10-04 | 2 | -10/+2 |
| * | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -68/+67 |
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| | * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -65/+65 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 1 | -0/+14 |
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| | * | Merge pull request #1422 from YosysHQ/eddie/aigmap_select | Clifford Wolf | 2019-10-03 | 1 | -6/+40 |
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| | | * | Add -select option to aigmap | Eddie Hung | 2019-09-30 | 1 | -6/+40 |
| | * | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 |
| | * | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 |
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| * | | No need to punch ports at all | Eddie Hung | 2019-09-30 | 1 | -13/+0 |
| * | | Resolve FIXME on calling proc just once | Eddie Hung | 2019-09-30 | 1 | -2/+2 |
| * | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 1 | -0/+8 |
| * | | Add comment | Eddie Hung | 2019-09-30 | 1 | -0/+1 |
| * | | scc call on active module module only, plus cleanup | Eddie Hung | 2019-09-30 | 1 | -21/+16 |
| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 1 | -1/+1 |
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| | * | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 1 | -1/+1 |
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| | | * | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 1 | -1/+1 |
| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 1 | -3/+16 |
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| | * | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 1 | -3/+16 |
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| | | * | "abc_padding" attr for blackbox outputs that were padded, remove them later | Eddie Hung | 2019-09-23 | 1 | -3/+16 |
| * | | | Fix "scc" call inside abc9 to consider all wires | Eddie Hung | 2019-09-29 | 1 | -1/+1 |
| * | | | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 1 | -78/+65 |
| * | | | Split ABC9 based on clocking only, add "abc_mergeability" attr for en | Eddie Hung | 2019-09-27 | 1 | -88/+28 |
