| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 2 | -2/+2 |
| * | Renamed "stdcells.v" to "techmap.v" | Clifford Wolf | 2014-07-31 | 3 | -6/+6 |
| * | Added "techmap -assert" | Clifford Wolf | 2014-07-31 | 1 | -13/+42 |
| * | Added techmap CONSTMAP feature | Clifford Wolf | 2014-07-30 | 1 | -10/+119 |
| * | Added "techmap -map %{design-name}" | Clifford Wolf | 2014-07-29 | 2 | -10/+19 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 3 | -7/+4 |
| * | Added techmap -extern | Clifford Wolf | 2014-07-27 | 1 | -16/+64 |
| * | Added topological sorting to techmap | Clifford Wolf | 2014-07-27 | 1 | -20/+52 |
| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 2 | -21/+19 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 6 | -21/+21 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 4 | -10/+10 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 3 | -12/+12 |
| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 3 | -17/+7 |
| * | More RTLIL::Cell API usage cleanups | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 6 | -16/+18 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 6 | -128/+128 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 6 | -128/+128 |
| * | Added copy-constructor-like module->addCell(name, other) method | Clifford Wolf | 2014-07-26 | 1 | -8/+4 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 6 | -122/+59 |
| * | Added "make SMALL=1" | Clifford Wolf | 2014-07-24 | 1 | -1/+4 |
| * | Added "make PRETTY=1" | Clifford Wolf | 2014-07-24 | 1 | -6/+6 |
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 2 | -131/+69 |
| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 3 | -25/+24 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 2 | -3/+3 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 2 | -3/+3 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 3 | -3/+3 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 4 | -78/+78 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 4 | -78/+78 |
| * | Replaced depricated NEW_WIRE macro with module->addWire() calls | Clifford Wolf | 2014-07-21 | 1 | -2/+2 |
| * | Removed deprecated module->new_wire() | Clifford Wolf | 2014-07-21 | 1 | -4/+4 |
| * | Added call_on_selection() and call_on_module() API | Clifford Wolf | 2014-07-20 | 1 | -9/+1 |
| * | Added support for "blackbox" attribute to iopadmap | Clifford Wolf | 2014-07-17 | 1 | -1/+1 |
| * | Added support for "blackbox" attribute to flatten/techmap | Clifford Wolf | 2014-07-17 | 1 | -1/+4 |
| * | be more verbose when techmap yielded processes | Johann Glaser | 2014-05-26 | 1 | -1/+5 |
| * | Merged OSX fixes from Siesh1oo with some modifications | Clifford Wolf | 2014-03-13 | 1 | -0/+1 |
| * | - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar... | Siesh1oo | 2014-03-12 | 1 | -1/+2 |
| * | OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/... | Clifford Wolf | 2014-03-11 | 1 | -2/+3 |
| * | Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 | 1 | -0/+1 |
| * | Fixed dumping of timing() { .. } block in libparse | Clifford Wolf | 2014-03-09 | 1 | -2/+3 |
| * | Added techmap -max_iter option | Clifford Wolf | 2014-03-06 | 1 | -0/+10 |
| * | Added _TECHMAP_REPLACE_ feature to techmap | Clifford Wolf | 2014-02-20 | 1 | -4/+21 |
| * | Added "extract -ignore_parameters" and "extract -ignore_param ..." | Clifford Wolf | 2014-02-20 | 1 | -0/+79 |
| * | Added "extract -map %<design_name>" | Clifford Wolf | 2014-02-20 | 1 | -10/+30 |
| * | Added techmap support for _TECHMAP_CONNMAP_*_ | Clifford Wolf | 2014-02-18 | 1 | -0/+39 |
| * | Better preserve wires when flattening (in comparison to techmap) | Clifford Wolf | 2014-02-17 | 1 | -12/+12 |
| * | Added some additional checks to techmap | Clifford Wolf | 2014-02-16 | 1 | -0/+14 |
| * | Added CONSTMSK and CONSTVAL feature to techmap | Clifford Wolf | 2014-02-16 | 1 | -0/+23 |
| * | Added recursion support to techmap | Clifford Wolf | 2014-02-16 | 1 | -260/+262 |
| * | Added iopadmap -bits | Clifford Wolf | 2014-02-15 | 1 | -14/+48 |
