iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-12/+1
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*	Added "techmap -autoproc"	Clifford Wolf	2014-09-01	1	-2/+18
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*	Fixed inserting of Q-inverters in dfflibmap	Clifford Wolf	2014-08-27	1	-0/+5
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*	Only call proc_share_dirname() in techmap when necessary	Clifford Wolf	2014-08-23	1	-2/+1
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*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	5	-32/+41
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*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-4/+5
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*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17	1	-1/+1
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*	Bugfix in iopadmap	Clifford Wolf	2014-08-15	1	-1/+3
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	2	-5/+5
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*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-3/+3
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*	document "techmap -map %<design-name>"	Clifford Wolf	2014-08-15	1	-0/+3
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*	Added module->ports	Clifford Wolf	2014-08-14	1	-2/+2
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*	Implemented recursive techmap	Clifford Wolf	2014-08-03	1	-16/+62
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*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02	1	-5/+40
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*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02	1	-0/+1
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	2	-3/+3
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	2	-4/+6
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	4	-38/+38
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	1	-6/+1
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	5	-98/+98
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-1/+1
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	2	-2/+2
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*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31	3	-6/+6
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*	Added "techmap -assert"	Clifford Wolf	2014-07-31	1	-13/+42
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-10/+119
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	2	-10/+19
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	3	-7/+4
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*	Added techmap -extern	Clifford Wolf	2014-07-27	1	-16/+64
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*	Added topological sorting to techmap	Clifford Wolf	2014-07-27	1	-20/+52
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	2	-21/+19
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	6	-21/+21
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	4	-10/+10
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	3	-12/+12
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	3	-17/+7
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-2/+2
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	6	-16/+18
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	6	-128/+128
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	6	-128/+128
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*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	1	-8/+4
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	6	-122/+59
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*	Added "make SMALL=1"	Clifford Wolf	2014-07-24	1	-1/+4
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*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-6/+6
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	2	-131/+69
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	3	-25/+24
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	2	-3/+3
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	2	-3/+3
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	3	-3/+3
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	4	-78/+78
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	4	-78/+78
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*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21	1	-2/+2
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