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* Remove abc9 -clk optionEddie Hung2019-12-301-1/+1
* abc9_ops -prep_dff cope with lack of holes moduleEddie Hung2019-12-301-38/+38
* Rename structEddie Hung2019-12-301-3/+3
* Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-301-9/+0
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| * Remove delay targets docEddie Hung2019-12-301-9/+0
* | Move Pass::call() out of abc9_ops into abc9Eddie Hung2019-12-302-68/+59
* | Use function argEddie Hung2019-12-301-9/+9
* | holes_module to be whiteboxEddie Hung2019-12-301-0/+10
* | Add abc9_ops -prep_holesEddie Hung2019-12-302-3/+313
* | Add abc9_ops -prep_dffEddie Hung2019-12-303-39/+50
* | Restore count_outputs, move process check to abcEddie Hung2019-12-302-11/+13
* | Fix struct nameEddie Hung2019-12-301-3/+3
* | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-302-323/+124
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| * write_xaiger to use scratchpad for stats; cleanup abc9Eddie Hung2019-12-301-173/+15
| * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-301-23/+68
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| * | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-301-49/+19
| * | GrammarEddie Hung2019-12-301-1/+1
| * | Disable clock domain partitioning in Yosys pass, let ABC do itEddie Hung2019-12-231-6/+22
| * | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-19/+18
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| * | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-191-5/+5
| * | | Remove &verify -sEddie Hung2019-12-171-1/+1
| * | | Use pool<> instead of std::set<> to preserver orderingEddie Hung2019-12-171-6/+6
| * | | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flopEddie Hung2019-12-161-5/+27
| * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-062-175/+137
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| * | | | Call abc9 with "&write -n", and parse_xaiger() to copeEddie Hung2019-12-061-2/+2
| * | | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type asEddie Hung2019-12-061-39/+15
| * | | | abc9 to do clock partitioning againEddie Hung2019-12-051-37/+144
| * | | | Add assertionEddie Hung2019-12-031-0/+1
| * | | | Add abc9_init wire, attach to abc9_flop cellEddie Hung2019-12-031-2/+12
| * | | | CleanupEddie Hung2019-12-011-3/+2
| * | | | Fix debugEddie Hung2019-11-251-3/+3
| * | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-251-0/+41
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| * | | | | abc9 to contain time callEddie Hung2019-11-251-1/+1
| * | | | | abc9 to no longer to clock partitioning, operate on whole modules onlyEddie Hung2019-11-251-139/+32
| * | | | | Conditioning abc9 on POs not accurate due to cellsEddie Hung2019-11-231-15/+6
| * | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-222-270/+0
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| | * | | | | Move clkpart into passes/hierarchyEddie Hung2019-11-222-270/+0
| * | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dffEddie Hung2019-11-221-8/+9
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| | * | | | | Only action if there is more than one clock domainEddie Hung2019-11-221-7/+8
| | * | | | | Replace TODOEddie Hung2019-11-221-1/+1
| * | | | | | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-222-1/+2
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| | * | | | | BracketsEddie Hung2019-11-221-1/+1
| | * | | | | Entry in Makefile.incEddie Hung2019-11-221-0/+1
| * | | | | | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-221-0/+268
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| | * | | | | New 'clkpart' to {,un}partition design according to clock/enableEddie Hung2019-11-221-0/+268
| * | | | | | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_Eddie Hung2019-11-211-1/+1
| * | | | | | endomain -> ctrldomainEddie Hung2019-11-201-3/+3
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-192-6/+11
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| * | | | | | Use "abc9_period" attribute for delay targetEddie Hung2019-10-071-3/+24
| * | | | | | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-30/+6