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* Clean up `passes/techmap/hilomap.cc`.Alberto Gonzalez2020-04-091-6/+2
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* Merge pull request #1865 from boqwxp/cleanup_dfflibmapwhitequark2020-04-061-27/+27
|\ | | | | Clean up `passes/techmap/dfflibmap.cc`.
| * Clean up `passes/techmap/dfflibmap.cc`.Alberto Gonzalez2020-04-061-27/+27
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* | Clean up `passes/techmap/extract.cc`.Alberto Gonzalez2020-04-051-43/+36
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* Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-0226-523/+523
|\ | | | | IdString: use more ID::*, make them easier to use, speed up IdString::in()
| * kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-0226-517/+515
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| * kernel: use more ID::*Eddie Hung2020-04-022-10/+12
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* | iopadmap: Fix z assignment to inout portMarcin Kościelnicki2020-04-021-1/+15
| | | | | | | | Fixes #1841.
* | Merge pull request #1842 from YosysHQ/mwk/fix-deminout-xzClaire Wolf2020-04-021-1/+1
|\ \ | |/ |/| deminout: prevent any constant assignment from demoting to input
| * deminout: prevent any constant assignment from demoting to inputMarcin Kościelnicki2020-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this patch, ``` module top(inout io); assign io = 1'bx; endmodule ``` would have the `io` pin demoted to input (same happens for `1'bz`, but not for `1'b0` or `1'b1`), resulting in check failures later on. Part of fix for #1841.
* | Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-023-4/+4
|\ \ | |/ |/| kernel: speedup by using more pass-by-const-ref
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-133-4/+4
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* | Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fixClaire Wolf2020-03-261-1/+1
|\ \ | | | | | | techmap: Fix cell names with _TECHMAP_REPLACE_.*
| * | techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-1/+1
| |/ | | | | | | Fixes #1804.
* / iopadmap: Attempt to give new wires/cells meaningful namesR. Ou2020-03-221-6/+18
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* Merge pull request #1743 from YosysHQ/eddie/abc9_keepEddie Hung2020-03-112-13/+15
|\ | | | | abc9: improve (* keep *) handling
| * abc9: for sccs, create a new wire instead of using entirety of existingEddie Hung2020-03-061-7/+7
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| * abc9: (* keep *) wires to be PO only, not PI as well; fix scc handlingEddie Hung2020-03-061-8/+5
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| * abc: add abc.debug scratchpad optionEddie Hung2020-03-061-0/+5
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* | Merge pull request #1753 from YosysHQ/dave/abc9-speedupDavid Shah2020-03-101-7/+7
|\ \ | | | | | | Add ScriptPass::run_nocheck and use for abc9
| * | Add ScriptPass::run_nocheck and use for abc9David Shah2020-03-091-7/+7
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1721 from YosysHQ/dave/tribuf-unusedDavid Shah2020-03-101-2/+1
|\ \ | |/ |/| deminout: Don't demote inouts with unused bits
| * deminout: Don't demote inouts with unused bitsDavid Shah2020-03-041-2/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-021-14/+54
| | | | | | | | | | iopadmap: Look harder for already-present buffers. Fixes #1720.
* | Fixes for older compilersEddie Hung2020-02-271-1/+1
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* | abc9_ops: suppress -prep_box warning for abc9_flopEddie Hung2020-02-271-1/+1
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* | Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-271-3/+3
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* | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-271-3/+4
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* | Fix spacingEddie Hung2020-02-271-18/+18
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* | abc9_ops: still emit delay table even box has no timingEddie Hung2020-02-271-3/+1
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* | abc9_ops: demote lack of box timing info to warningEddie Hung2020-02-271-2/+4
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* | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-89/+15
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* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-24/+18
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* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-72/+53
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* | abc9_ops: add and use new TimingInfo structEddie Hung2020-02-271-70/+41
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* | abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-272-64/+64
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* | abc9_ops: sort LUT delays to be ascendingEddie Hung2020-02-271-1/+4
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* | abc9_ops: output LUT areaEddie Hung2020-02-271-6/+6
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* | abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTsEddie Hung2020-02-271-18/+33
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* | xilinx: improve specify functionalityEddie Hung2020-02-271-19/+19
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* | xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-158/+264
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* | Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-271-40/+117
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* | abc9_ops: assert on $specify2 propertiesEddie Hung2020-02-271-0/+3
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* | abc9_ops: -prep_box, to be called onceEddie Hung2020-02-272-50/+49
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* | abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-272-6/+115
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* | Merge pull request #1709 from rqou/coolrunner2_counterClaire Wolf2020-02-271-97/+354
|\ \ | |/ |/| Improve CoolRunner-II optimization by using extract_counter pass
| * extract_counter: Implement extracting up countersR. Ou2020-02-171-65/+247
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| * extract_counter: Add support for inverted clock enableR. Ou2020-02-171-8/+28
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| * extract_counter: Fix clock enableR. Ou2020-02-171-1/+3
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| * extract_counter: Fix outputting count to module portR. Ou2020-02-171-8/+20
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