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Commit message (
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Author
Age
Files
Lines
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-2
/
+2
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-2
/
+2
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-2
/
+2
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
1
-8
/
+2
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
1
-14
/
+12
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
1
-1
/
+1
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-1
/
+1
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-1
/
+1
*
Replaced depricated NEW_WIRE macro with module->addWire() calls
Clifford Wolf
2014-07-21
1
-2
/
+2
*
Added hilomap command
Clifford Wolf
2014-01-19
1
-0
/
+129