Use only module->addCell() and module->remove() to create and delete cells

1 files changed, 2 insertions, 8 deletions

diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index 51b8802c4..e41536707 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -34,22 +34,16 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 		if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
 			if (!singleton_mode || last_hi == RTLIL::State::Sm) {
 				last_hi = module->addWire(NEW_ID);
-				RTLIL::Cell *cell = new RTLIL::Cell;
-				cell->name = NEW_ID;
-				cell->type = RTLIL::escape_id(hicell_celltype);
+				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
 				cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi;
-				module->add(cell);
 			}
 			bit = last_hi;
 		}
 		if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
 			if (!singleton_mode || last_lo == RTLIL::State::Sm) {
 				last_lo = module->addWire(NEW_ID);
-				RTLIL::Cell *cell = new RTLIL::Cell;
-				cell->name = NEW_ID;
-				cell->type = RTLIL::escape_id(locell_celltype);
+				RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
 				cell->connections[RTLIL::escape_id(locell_portname)] = last_lo;
-				module->add(cell);
 			}
 			bit = last_lo;
 		}