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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Fixes in "hilomap" help messageClifford Wolf2014-10-081-4/+2
* namespace YosysClifford Wolf2014-09-271-0/+4
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-2/+2
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-2/+2
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-2/+2
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-8/+2
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-14/+12
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-1/+1
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-1/+1
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-211-2/+2
* Added hilomap commandClifford Wolf2014-01-191-0/+129