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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Added missing dont_use handling for SR FFs to dfflibmapClifford Wolf2018-04-051-0/+4
* updated to use get_src_attribute() and set_src_attribute().Jason Lowdermilk2017-08-311-2/+2
* Add support for source line tracking through synthesis phaseJason Lowdermilk2017-08-291-0/+4
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Prefer noninverting FFs in dfflibmapClifford Wolf2016-04-051-4/+20
* Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)Clifford Wolf2016-02-011-8/+68
* Added support for "dfflibmap -liberty +/..."Clifford Wolf2015-09-181-0/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-5/+5
* Added liberty dont_use support to dfflibmapClifford Wolf2015-05-311-0/+4
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-241-2/+6
* Added "dfflibmap -prepare" helpClifford Wolf2014-12-241-1/+5
* Added "dfflibmap -prepare"Clifford Wolf2014-12-241-31/+54
* Fixed various VS warningsClifford Wolf2014-10-181-4/+4
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-1/+1
* namespace YosysClifford Wolf2014-09-271-1/+3
* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-271-0/+5
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-231-3/+4
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-1/+1
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-2/+2
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-1/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-2/+2
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-20/+15
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-111-0/+1
* Fixed dfflibmap for cell libraries with no set-reset-ffClifford Wolf2014-02-151-1/+1
* renamed LibertyParer to LibertyParserClifford Wolf2014-01-141-1/+1
* Fixed dfflibmap for unused output portsClifford Wolf2013-12-211-0/+1
* Now prefer smallest cells in dfflibmapClifford Wolf2013-12-211-2/+22
* Cleanup of dfflibmap cellmap exploration codeClifford Wolf2013-12-201-17/+20
* Further improved dfflibmap cellmap explorationClifford Wolf2013-12-201-14/+18
* Fixed dfflibmap endless-loop bugClifford Wolf2013-12-201-0/+1
* Prefer non-inverted clocks in dfflibmapClifford Wolf2013-12-191-6/+8
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-221-1/+1
* Added placeholder check to dfflibmap and cleaned up some other placeholder ch...Clifford Wolf2013-10-311-1/+1
* Added support for sr flip-flops to dfflibmapClifford Wolf2013-10-241-3/+168
* Moved dfflibmap from passes/dfflibmap to passes/techmapClifford Wolf2013-10-161-0/+342