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| author | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-31 14:51:56 -0600 |
|---|---|---|
| committer | Jason Lowdermilk <jlowder@chipscan.us> | 2017-08-31 14:51:56 -0600 |
| commit | 8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a (patch) | |
| tree | aa6377e3fd95214735bca3b6c3fe920b78e29f08 /passes/techmap/dfflibmap.cc | |
| parent | 71d43cfc08b1949d5d07d6715107cd87c40e4465 (diff) | |
| download | yosys-8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a.tar.gz yosys-8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a.tar.bz2 yosys-8dc6083de7c0328a8cd1d6e7b76dfd528b7baa3a.zip | |
updated to use get_src_attribute() and set_src_attribute().
Diffstat (limited to 'passes/techmap/dfflibmap.cc')
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 71d708c18..4cb1489a8 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -478,14 +478,14 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare auto cell_type = cell->type; auto cell_name = cell->name; auto cell_connections = cell->connections(); - std::string src = cell->attributes["\\src"].decode_string(); + std::string src = cell->get_src_attribute(); module->remove(cell); cell_mapping &cm = cell_mappings[cell_type]; RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name); - if (!src.empty()) new_cell->attributes["\\src"] = src; + new_cell->set_src_attribute(src); bool has_q = false, has_qn = false; for (auto &port : cm.ports) { |