iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Clean up some whitepsace outliers	Larry Doolittle	2019-02-26	1	-2/+2
*	DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/...	Niels Moseley	2018-11-06	1	-1/+10
*	Report an error when a liberty file contains pin references that reference no...	Niels Moseley	2018-11-03	1	-0/+3
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Added missing dont_use handling for SR FFs to dfflibmap	Clifford Wolf	2018-04-05	1	-0/+4
*	updated to use get_src_attribute() and set_src_attribute().	Jason Lowdermilk	2017-08-31	1	-2/+2
*	Add support for source line tracking through synthesis phase	Jason Lowdermilk	2017-08-29	1	-0/+4
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Prefer noninverting FFs in dfflibmap	Clifford Wolf	2016-04-05	1	-4/+20
*	Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)	Clifford Wolf	2016-02-01	1	-8/+68
*	Added support for "dfflibmap -liberty +/..."	Clifford Wolf	2015-09-18	1	-0/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-5/+5
*	Added liberty dont_use support to dfflibmap	Clifford Wolf	2015-05-31	1	-0/+4
*	Added ENABLE_NDEBUG makefile options	Clifford Wolf	2015-01-24	1	-2/+6
*	Added "dfflibmap -prepare" help	Clifford Wolf	2014-12-24	1	-1/+5
*	Added "dfflibmap -prepare"	Clifford Wolf	2014-12-24	1	-31/+54
*	Fixed various VS warnings	Clifford Wolf	2014-10-18	1	-4/+4
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-1/+3
*	Fixed inserting of Q-inverters in dfflibmap	Clifford Wolf	2014-08-27	1	-0/+5
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	1	-3/+4
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-2/+2
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-1/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-2/+2
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-2/+2
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-20/+15
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-0/+1
*	Fixed dfflibmap for cell libraries with no set-reset-ff	Clifford Wolf	2014-02-15	1	-1/+1
*	renamed LibertyParer to LibertyParser	Clifford Wolf	2014-01-14	1	-1/+1
*	Fixed dfflibmap for unused output ports	Clifford Wolf	2013-12-21	1	-0/+1
*	Now prefer smallest cells in dfflibmap	Clifford Wolf	2013-12-21	1	-2/+22
*	Cleanup of dfflibmap cellmap exploration code	Clifford Wolf	2013-12-20	1	-17/+20
*	Further improved dfflibmap cellmap exploration	Clifford Wolf	2013-12-20	1	-14/+18
*	Fixed dfflibmap endless-loop bug	Clifford Wolf	2013-12-20	1	-0/+1
*	Prefer non-inverted clocks in dfflibmap	Clifford Wolf	2013-12-19	1	-6/+8
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-1/+1
*	Added placeholder check to dfflibmap and cleaned up some other placeholder ch...	Clifford Wolf	2013-10-31	1	-1/+1
*	Added support for sr flip-flops to dfflibmap	Clifford Wolf	2013-10-24	1	-3/+168
*	Moved dfflibmap from passes/dfflibmap to passes/techmap	Clifford Wolf	2013-10-16	1	-0/+342