iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
\| \| \| \| \| \| \| \|	s/((Claire\|Xen\|Xenia\|Clifford)\s+)+(Wolf\|Xen)\s+<(claire\|clifford)@(symbioticeda.com\|clifford.at\|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina\|Nak\|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com\|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave\|david)@(symbioticeda.com\|yosyshq.com\|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag\|micko)@(symbioticeda.com\|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
*	clkbufmap: improve input pad handling.	Marcelina Kościelnicka	2020-07-09	1	-17/+39
\| \| \| \| \| \|	- allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
*	Naming fixes.	Marcelina Kościelnicka	2020-07-05	1	-1/+1
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*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
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*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-6/+4
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*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-3/+5
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*	clkbufmap: Add support for inverters in clock path.	Marcin Kościelnicki	2019-11-25	1	-0/+41
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*	improve clkbuf_inhibit propagation upwards through hierarchy	Marcin Kościelnicki	2019-08-27	1	-1/+12
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*	clkbufmap to only check clkbuf_inhibit if no selection given	Eddie Hung	2019-08-23	1	-5/+18
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*	Review comment from @cliffordwolf	Eddie Hung	2019-08-23	1	-1/+2
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*	move attributes to wires	Marcin Kościelnicki	2019-08-13	1	-19/+5
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*	review fixes	Marcin Kościelnicki	2019-08-13	1	-15/+3
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*	Add clock buffer insertion pass, improve iopadmap.	Marcin Kościelnicki	2019-08-13	1	-0/+299
	A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.