review fixes

1 files changed, 3 insertions, 15 deletions

diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc
index 9ecc83071..a2d10c48b 100644
--- a/passes/techmap/clkbufmap.cc
+++ b/passes/techmap/clkbufmap.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2019  Marcin Kościelnicki <mwk@0x04.net>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -32,19 +33,6 @@ void split_portname_pair(std::string &port1, std::string &port2)
 	}
 }
 
-std::vector<std::string> split(std::string text, const char *delim)
-{
-	std::vector<std::string> list;
-	char *p = strdup(text.c_str());
-	char *t = strtok(p, delim);
-	while (t != NULL) {
-		list.push_back(t);
-		t = strtok(NULL, delim);
-	}
-	free(p);
-	return list;
-}
-
 struct ClkbufmapPass : public Pass {
 	ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { }
 	void help() YS_OVERRIDE
@@ -127,7 +115,7 @@ struct ClkbufmapPass : public Pass {
 				auto it = module->attributes.find("\\clkbuf_driver");
 				if (it != module->attributes.end()) {
 					auto value = it->second.decode_string();
-					for (auto name : split(value, ",")) {
+					for (auto name : split_tokens(value, ",")) {
 						auto wire = module->wire(RTLIL::escape_id(name));
 						if (!wire)
 							log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));
@@ -138,7 +126,7 @@ struct ClkbufmapPass : public Pass {
 				it = module->attributes.find("\\clkbuf_sink");
 				if (it != module->attributes.end()) {
 					auto value = it->second.decode_string();
-					for (auto name : split(value, ",")) {
+					for (auto name : split_tokens(value, ",")) {
 						auto wire = module->wire(RTLIL::escape_id(name));
 						if (!wire)
 							log_error("Module %s does not have port %s.\n", log_id(module), log_id(name));