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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:03:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 10:03:41 -0700 |
| commit | 4d89c3f468b6090dceabb304b9f56f3a6a597057 (patch) | |
| tree | f361abf471a91bf094bd33dc0a494be46d46f564 /passes/techmap/clkbufmap.cc | |
| parent | 6872805a3eb738a0a5921b232022abfd507cebb8 (diff) | |
| download | yosys-4d89c3f468b6090dceabb304b9f56f3a6a597057.tar.gz yosys-4d89c3f468b6090dceabb304b9f56f3a6a597057.tar.bz2 yosys-4d89c3f468b6090dceabb304b9f56f3a6a597057.zip | |
Review comment from @cliffordwolf
Diffstat (limited to 'passes/techmap/clkbufmap.cc')
| -rw-r--r-- | passes/techmap/clkbufmap.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 6fac1b437..55341ead0 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -112,7 +112,8 @@ struct ClkbufmapPass : public Pass { for (auto module : modules_sorted) { if (module->get_blackbox_attribute()) { - for (auto wire : module->wires()) { + for (auto port : module->ports) { + auto wire = module->wire(port); if (wire->get_bool_attribute("\\clkbuf_driver")) for (int i = 0; i < GetSize(wire); i++) buf_ports.insert(make_pair(module->name, make_pair(wire->name, i))); |