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path: root/passes/techmap/abc9.cc
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* Add commentEddie Hung2019-07-131-0/+5
* duplicate -> cloneEddie Hung2019-07-121-3/+3
* More cleanupEddie Hung2019-07-121-8/+2
* CleanupEddie Hung2019-07-121-29/+51
* CleanupEddie Hung2019-07-121-10/+4
* CleanupEddie Hung2019-07-121-15/+24
* More cleanupEddie Hung2019-07-121-11/+10
* CleanupEddie Hung2019-07-121-46/+16
* CleanupEddie Hung2019-07-121-7/+1
* CleanupEddie Hung2019-07-121-13/+109
* Enable &mfs for abc9, even if it only currently works for ice40Eddie Hung2019-07-111-1/+1
* Fix spacingEddie Hung2019-06-281-2/+2
* Do not use Module::remove() iterator versionEddie Hung2019-06-271-5/+6
* Remove &retime when abc9 -fastEddie Hung2019-06-271-1/+1
* Cleanup abc9.ccEddie Hung2019-06-271-15/+17
* Fix spacingEddie Hung2019-06-261-38/+38
* Support more than one port in the abc_scc_break attrEddie Hung2019-06-261-38/+42
* nullptr checkEddie Hung2019-06-251-0/+1
* Fix for abc_scc_break is busEddie Hung2019-06-241-21/+23
* More meaningful error messageEddie Hung2019-06-241-0/+2
* Do not use log_id as it strips \\, also fix scc for |wire| > 1Eddie Hung2019-06-241-13/+30
* Fix abc9's scc breaker, also break on abc_scc_break attrEddie Hung2019-06-241-9/+31
* Do not rename non LUT cells in abc9Eddie Hung2019-06-211-11/+16
* Fix gcc warning of potentially uninitialisedEddie Hung2019-06-201-2/+2
* Fix simple_abc9/generate test with 1'bx at MSBEddie Hung2019-06-201-1/+1
* Do not call "setundef -zero" in abc9Eddie Hung2019-06-201-5/+2
* &scorr before &sweep, remove &retime as recommendedEddie Hung2019-06-171-1/+1
* Copy not move parameters/attributesEddie Hung2019-06-171-3/+4
* Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-171-25/+26
* Re-enable &dc2Eddie Hung2019-06-171-1/+1
* CleanupEddie Hung2019-06-161-51/+7
* Get rid of compiler warningsEddie Hung2019-06-141-5/+5
* Update abc9 -D docEddie Hung2019-06-141-1/+2
* Enable "abc9 -D <num>" for timing-driven synthesisEddie Hung2019-06-141-9/+9
* Further cleanup based on @daveshah1Eddie Hung2019-06-141-10/+0
* Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-06-141-0/+9
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| * ecp5: Add abc9 optionDavid Shah2019-06-141-0/+9
* | Remove extra semicolonEddie Hung2019-06-141-1/+1
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* Rip out all non FPGA stuff from abc9Eddie Hung2019-06-121-343/+111
* Be more precise when connecting during ABC9 re-integrationEddie Hung2019-06-121-1/+3
* Remove hacky wideports_split from abc9Eddie Hung2019-06-121-52/+4
* Fix compile errors when #if 1 for debugEddie Hung2019-06-121-7/+8
* Do not call abc9 if no outputsEddie Hung2019-06-121-54/+65
* More write_xaiger cleanupEddie Hung2019-06-121-1/+1
* ConsistencyEddie Hung2019-06-121-1/+1
* Typo: wire delay is -W argumentEddie Hung2019-06-121-1/+1
* Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-5/+13
* Fine tune aigerparseEddie Hung2019-06-071-1/+5
* Remove dupeEddie Hung2019-06-031-7/+7
* Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-6/+0
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