diff options
author | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 13:19:45 -0700 |
---|---|---|
committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 13:19:45 -0700 |
commit | 63fc879a5f698803d563a57275cc99a3df2d1414 (patch) | |
tree | 323d48e1122854904f62e19030dd021fbc434854 /passes/techmap/abc9.cc | |
parent | b45d06d7a334c4b18e44793b33aaffcaf1f04b21 (diff) | |
download | yosys-63fc879a5f698803d563a57275cc99a3df2d1414.tar.gz yosys-63fc879a5f698803d563a57275cc99a3df2d1414.tar.bz2 yosys-63fc879a5f698803d563a57275cc99a3df2d1414.zip |
Copy not move parameters/attributes
Diffstat (limited to 'passes/techmap/abc9.cc')
-rw-r--r-- | passes/techmap/abc9.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 9c4e6bb39..184fbfaee 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -599,11 +599,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; RTLIL::Cell *existing_cell = module->cell(c->name); if (existing_cell) { - cell->parameters = std::move(existing_cell->parameters); - cell->attributes = std::move(existing_cell->attributes); + cell->parameters = existing_cell->parameters; + cell->attributes = existing_cell->attributes; } else { - cell->parameters = std::move(c->parameters); + cell->parameters = c->parameters; + cell->attributes = c->attributes; } for (auto &conn : c->connections()) { RTLIL::SigSpec newsig; |