| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename "singleton" pass to "uniquify" | Clifford Wolf | 2017-08-20 | 1 | -1/+1 |
| * | Add "sim -zinit -rstlen" | Clifford Wolf | 2017-08-18 | 1 | -1/+53 |
| * | Add "sim" support for memories | Clifford Wolf | 2017-08-18 | 1 | -2/+136 |
| * | Add support for assert/assume/cover to "sim" command | Clifford Wolf | 2017-08-18 | 1 | -4/+47 |
| * | Add writeback mode to "sim" command | Clifford Wolf | 2017-08-17 | 1 | -0/+44 |
| * | Improve "sim" command | Clifford Wolf | 2017-08-17 | 1 | -54/+272 |
| * | Add "sim" command skeleton | Clifford Wolf | 2017-08-16 | 1 | -0/+371 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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