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author | Clifford Wolf <clifford@clifford.at> | 2017-08-18 12:54:17 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-08-18 12:54:17 +0200 |
commit | bbdf7d9c66359fa4210477fd998a534fc9900392 (patch) | |
tree | c15c5c0d6d792ccaee77d9bcdedc712c59de4b2e /passes/sat/sim.cc | |
parent | 35760dd784f4b2e360a4137ce115104d1204d7a6 (diff) | |
download | yosys-bbdf7d9c66359fa4210477fd998a534fc9900392.tar.gz yosys-bbdf7d9c66359fa4210477fd998a534fc9900392.tar.bz2 yosys-bbdf7d9c66359fa4210477fd998a534fc9900392.zip |
Add "sim -zinit -rstlen"
Diffstat (limited to 'passes/sat/sim.cc')
-rw-r--r-- | passes/sat/sim.cc | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index a80d89a81..966510776 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -29,8 +29,22 @@ struct SimShared bool debug = false; bool hide_internal = true; bool writeback = false; + bool zinit = false; + int rstlen = 1; }; +void zinit(State &v) +{ + if (v != State::S1) + v = State::S0; +} + +void zinit(Const &v) +{ + for (auto &bit : v.bits) + zinit(bit); +} + struct SimInstance { SimShared *shared; @@ -148,6 +162,27 @@ struct SimInstance formal_database.insert(cell); } } + + if (shared->zinit) + { + for (auto &it : ff_database) + { + Cell *cell = it.first; + ff_state_t &ff = it.second; + zinit(ff.past_d); + + SigSpec qsig = cell->getPort("\\Q"); + Const qdata = get_state(qsig); + zinit(qdata); + set_state(qsig, qdata); + } + + for (auto &it : mem_database) { + mem_state_t &mem = it.second; + zinit(mem.past_wr_en); + zinit(mem.data); + } + } } ~SimInstance() @@ -663,6 +698,9 @@ struct SimWorker : SimShared set_inports(reset, State::S1); set_inports(resetn, State::S0); + set_inports(clock, State::Sx); + set_inports(clockn, State::Sx); + update(); write_vcd_header(); @@ -687,7 +725,7 @@ struct SimWorker : SimShared set_inports(clock, State::S1); set_inports(clockn, State::S0); - if (cycle == 0) { + if (cycle+1 == rstlen) { set_inports(reset, State::S0); set_inports(resetn, State::S1); } @@ -730,6 +768,12 @@ struct SimPass : public Pass { log(" -resetn <portname>\n"); log(" name of top-level inverted reset input (active low)\n"); log("\n"); + log(" -rstlen <integer>\n"); + log(" number of cycles reset should stay active (default: 1)\n"); + log("\n"); + log(" -zinit\n"); + log(" zero-initialize all uninitialized regs and memories\n"); + log("\n"); log(" -n <integer>\n"); log(" number of cycles to simulate (default: 20)\n"); log("\n"); @@ -760,6 +804,10 @@ struct SimPass : public Pass { numcycles = atoi(args[++argidx].c_str()); continue; } + if (args[argidx] == "-rstlen" && argidx+1 < args.size()) { + worker.rstlen = atoi(args[++argidx].c_str()); + continue; + } if (args[argidx] == "-clock" && argidx+1 < args.size()) { worker.clock.insert(RTLIL::escape_id(args[++argidx])); continue; @@ -788,6 +836,10 @@ struct SimPass : public Pass { worker.writeback = true; continue; } + if (args[argidx] == "-zinit") { + worker.zinit = true; + continue; + } break; } extra_args(args, argidx, design); |