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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-42/+42
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+13
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-42/+42
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-42/+42
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-6/+2
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-5/+5
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-5/+5
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-231-4/+4
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-22/+22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-22/+22
* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-13/+13
* Wider range of cell types supported in "share" passClifford Wolf2014-07-211-17/+197
* Use ezSAT::non_incremental() in "share" passClifford Wolf2014-07-211-0/+2
* Added support for resource sharing in mux control logicClifford Wolf2014-07-201-86/+155
* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-201-4/+0
* Fixed creation of shift supercells in "share" passClifford Wolf2014-07-201-4/+20
* Added "share" supercell creationClifford Wolf2014-07-201-1/+115
* Added removing of always inactive cells to "share" passClifford Wolf2014-07-201-8/+42
* Progress in "share" passClifford Wolf2014-07-201-112/+185
* Progress in "share" passClifford Wolf2014-07-201-19/+56
* Started to implement real resource sharingClifford Wolf2014-07-191-0/+443