iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-6/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-5/+5
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-5/+5
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	Clifford Wolf	2014-07-23	1	-4/+4
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-22/+22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-22/+22
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-13/+13
*	Wider range of cell types supported in "share" pass	Clifford Wolf	2014-07-21	1	-17/+197
*	Use ezSAT::non_incremental() in "share" pass	Clifford Wolf	2014-07-21	1	-0/+2
*	Added support for resource sharing in mux control logic	Clifford Wolf	2014-07-20	1	-86/+155
*	Supercell creation for $div/$mod worked all along, fixed test benches	Clifford Wolf	2014-07-20	1	-4/+0
*	Fixed creation of shift supercells in "share" pass	Clifford Wolf	2014-07-20	1	-4/+20
*	Added "share" supercell creation	Clifford Wolf	2014-07-20	1	-1/+115
*	Added removing of always inactive cells to "share" pass	Clifford Wolf	2014-07-20	1	-8/+42
*	Progress in "share" pass	Clifford Wolf	2014-07-20	1	-112/+185
*	Progress in "share" pass	Clifford Wolf	2014-07-20	1	-19/+56
*	Started to implement real resource sharing	Clifford Wolf	2014-07-19	1	-0/+443