iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Update from master	Eddie Hung	2019-05-28	1	-1/+1
*	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-05-21	1	-1/+1
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\| *	Fix bug in "expose -input"	Clifford Wolf	2019-05-06	1	-1/+1
* \|	expose command to not skip 'internal' wires beginning with '$'	Eddie Hung	2019-02-16	1	-1/+1
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*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Add "expose -input"	Clifford Wolf	2018-03-12	1	-8/+43
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24	1	-10/+10
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-2/+2
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-7/+11
*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	1	-1/+1
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-25/+25
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-24/+24
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-6/+6
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-9/+9
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-11/+11
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-42/+13
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-1/+1
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-2/+2
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-3/+3
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-36/+36
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-36/+36
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-14/+7
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-1/+1
*	added log_header to miter and expose pass, show cell type for exposed ports	Johann Glaser	2014-05-28	1	-3/+5
*	Various improvements in expose command (added -sep and -cut)	Clifford Wolf	2014-02-09	1	-36/+119
*	Fixed handling of async reset in expose -evert-dff	Clifford Wolf	2014-02-08	1	-0/+1
*	Implemented expose -evert-dff	Clifford Wolf	2014-02-08	1	-11/+301
*	Added expose -dff	Clifford Wolf	2014-02-06	1	-1/+44
*	Added expose command	Clifford Wolf	2014-02-05	1	-0/+263