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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:57:57 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
commit | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (patch) | |
tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/sat/expose.cc | |
parent | b7dda723022ad00c6c0089be888eab319953faa8 (diff) | |
download | yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.gz yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.bz2 yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.zip |
Manual fixes for new cell connections API
Diffstat (limited to 'passes/sat/expose.cc')
-rw-r--r-- | passes/sat/expose.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 58dcf915f..a84faf792 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -485,12 +485,12 @@ struct ExposePass : public Pass { for (auto &it : module->cells) { if (!ct.cell_known(it.second->type)) continue; - for (auto &conn : it.second->connections()) + for (auto &conn : it.second->connections_) if (ct.cell_input(it.second->type, conn.first)) conn.second = out_to_in_map(sigmap(conn.second)); } - for (auto &conn : module->connections()) + for (auto &conn : module->connections_) conn.second = out_to_in_map(sigmap(conn.second)); } @@ -518,7 +518,7 @@ struct ExposePass : public Pass { for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++); - cell->get("\\Q") = cell_q_bits; + cell->set("\\Q", cell_q_bits); } RTLIL::Wire *wire_q = new RTLIL::Wire; |