| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -7/+11 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -15/+15 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -2/+2 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -7/+6 |
| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -12/+3 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -2/+9 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -15/+15 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -15/+15 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -14/+3 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 | 1 | -2/+2 |
| * | Fixed memory corruption with new SigSpec API in proc_mux | Clifford Wolf | 2014-07-22 | 1 | -7/+3 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -22/+22 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -22/+22 |
| * | Tiny cleanup in proc_mux.cc | Clifford Wolf | 2014-01-03 | 1 | -3/+0 |
| * | Fixed handling of boolean attributes (passes) | Clifford Wolf | 2013-10-24 | 1 | -1/+1 |
| * | Added help messages to proc_* passes | Clifford Wolf | 2013-03-01 | 1 | -3/+15 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+294 |
