iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-14/+14
*	kernel: use more ID::*	Eddie Hung	2020-04-02	1	-19/+19
*	proc_mux: consider \src attribute on CaseRule.	whitequark	2019-07-08	1	-10/+16
*	Improve proc full_case detection and handling, fixes #931	Clifford Wolf	2019-04-18	1	-0/+50
*	Revert #895	Eddie Hung	2019-04-16	1	-28/+0
*	proc_mux: Fix crash when trying to optimize non-existant mux to shiftx	Sylvain Munaut	2019-04-03	1	-1/+1
*	Create one $shiftx per bit in width	Eddie Hung	2019-03-25	1	-10/+17
*	Add a pmux-to-shiftx optimisation to proc_mux	Eddie Hung	2019-03-23	1	-0/+21
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Added "proc_mux -ifx"	Clifford Wolf	2016-06-06	1	-17/+31
*	Fixed proc_mux performance bug	Clifford Wolf	2016-04-25	1	-0/+3
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Improved proc_mux performance for huge always blocks	Clifford Wolf	2015-12-02	1	-36/+153
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-7/+11
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-15/+15
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-2/+2
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-7/+6
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-5/+5
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-12/+3
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-2/+9
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-15/+15
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-15/+15
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-14/+3
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Fixed memory corruption with new SigSpec API in proc_mux	Clifford Wolf	2014-07-22	1	-7/+3
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-22/+22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-22/+22
*	Tiny cleanup in proc_mux.cc	Clifford Wolf	2014-01-03	1	-3/+0
*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24	1	-1/+1
*	Added help messages to proc_* passes	Clifford Wolf	2013-03-01	1	-3/+15
*	initial import	Clifford Wolf	2013-01-05	1	-0/+294