iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Make liberal use of IdString.in()	Eddie Hung	2019-08-06	1	-2/+2
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*	proc_prune: promote assigns to module connections when legal.	whitequark	2019-07-09	1	-1/+1
\| \| \| \| \| \| \| \| \| \|	This can pave the way for further transformations by exposing identities that were previously hidden in a process to any pass that uses SigMap. Indeed, this commit removes some ad-hoc logic from proc_init that appears to have been tailored to the output of genrtlil in favor of using `SigMap.apply()`. (This removal is not optional, as the ad-hoc logic cannot cope with the result of running proc_prune; a similar issue was fixed in proc_arst.)
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
\| \| \| \| \| \| \| \| \|	o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -- c++ -- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
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*	Minor fixes in handling of "init" attribute	Clifford Wolf	2015-04-09	1	-0/+5
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*	Removed SigSpec::extend_xx() api	Clifford Wolf	2015-01-01	1	-1/+1
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*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-1/+1
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-5/+10
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-22/+22
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-10/+15
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-2/+2
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-22/+22
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-22/+22
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-5/+3
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	1	-1/+1
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-9/+9
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-9/+9
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*	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	Clifford Wolf	2014-02-21	1	-2/+6
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-2/+2
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*	Added "proc_arst -global_arst" feature	Clifford Wolf	2013-11-20	1	-5/+59
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*	Added handling of multiple async paths in proc_arst	Clifford Wolf	2013-10-19	1	-0/+12
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*	Added nosync attribute and some async reset related fixes	Clifford Wolf	2013-03-25	1	-0/+5
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*	Added help messages to proc_* passes	Clifford Wolf	2013-03-01	1	-6/+19
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+191