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| author | whitequark <whitequark@whitequark.org> | 2019-07-09 08:14:52 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-07-09 09:30:58 +0000 |
| commit | 44bcb7a187ffa00921cb14fa50428ce272ce3b6b (patch) | |
| tree | b9f0636001c8fb2464afdbcc5521fc07d0ea5ff0 /passes/proc/proc_arst.cc | |
| parent | 5fe0ffe30f315d50b2405c2d436ad8e7ca9ba2f6 (diff) | |
| download | yosys-44bcb7a187ffa00921cb14fa50428ce272ce3b6b.tar.gz yosys-44bcb7a187ffa00921cb14fa50428ce272ce3b6b.tar.bz2 yosys-44bcb7a187ffa00921cb14fa50428ce272ce3b6b.zip | |
proc_prune: promote assigns to module connections when legal.
This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)
Diffstat (limited to 'passes/proc/proc_arst.cc')
| -rw-r--r-- | passes/proc/proc_arst.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index b69eba3f9..d069f152a 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -172,7 +172,7 @@ restart_proc_arst: sync->type = sync->type == RTLIL::SyncType::STp ? RTLIL::SyncType::ST1 : RTLIL::SyncType::ST0; } for (auto &action : sync->actions) { - RTLIL::SigSpec rspec = action.second; + RTLIL::SigSpec rspec = assign_map(action.second); RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size()); for (int i = 0; i < GetSize(rspec); i++) if (rspec[i].wire == NULL) |