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* Make liberal use of IdString.in()Eddie Hung2019-08-061-2/+2
* proc_prune: promote assigns to module connections when legal.whitequark2019-07-091-1/+1
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-091-0/+5
* Removed SigSpec::extend_xx() apiClifford Wolf2015-01-011-1/+1
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-1/+1
* namespace YosysClifford Wolf2014-09-271-5/+10
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-22/+22
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-10/+15
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-2/+2
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-22/+22
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-22/+22
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-5/+3
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-9/+9
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-9/+9
* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-211-2/+6
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-271-2/+2
* Added "proc_arst -global_arst" featureClifford Wolf2013-11-201-5/+59
* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-191-0/+12
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-251-0/+5
* Added help messages to proc_* passesClifford Wolf2013-03-011-6/+19
* initial importClifford Wolf2013-01-051-0/+191