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* fixed invalid charMiodrag Milanovic2019-12-251-1/+1
* Minor nit fixesMarcin Kościelnicki2019-12-251-2/+2
* Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG tooEddie Hung2019-12-231-8/+18
* Fix CEA/CEB checkEddie Hung2019-12-231-2/+2
* Fix checking CE[AB] and for direct connectionsEddie Hung2019-12-231-18/+40
* Support unregistered cascades for A and B inputsEddie Hung2019-12-231-47/+74
* Add DSP48A* PCOUT -> PCIN cascade supportEddie Hung2019-12-231-10/+10
* xilinx_dsp: Initial DSP48A/DSP48A1 support.Marcin Kościelnicki2019-12-224-11/+886
* ice40_wrapcarry -unwrap to preserve 'src' attributeEddie Hung2019-12-091-1/+9
* -unwrap to create $lut not SB_LUT4 for opt_lutEddie Hung2019-12-091-7/+5
* Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-7/+11
* ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-17/+55
* Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-061-0/+8
* Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+1
* ice40_wrapcarry to preserve SB_CARRY's attributesEddie Hung2019-12-031-0/+2
* Check for either sign or zero extension for postAdd packingEddie Hung2019-11-261-3/+3
* Fix #1462, #1480.Marcin Kościelnicki2019-11-192-9/+11
* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-2/+2
* Fix dffmux peepopt init handlingClifford Wolf2019-10-162-27/+113
* Move GENERATE_PATTERN macro to separate utility headerClifford Wolf2019-10-163-128/+157
* Disable left-over log_debug in peepopt_dffmux.pmgClifford Wolf2019-10-161-1/+1
* Merge pull request #1432 from YosysHQ/eddie/fix1427Eddie Hung2019-10-081-47/+81
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| * Fix broken CI, check reset even for constants, trim rstmuxEddie Hung2019-10-021-23/+26
| * Refactor peepopt_dffmux and be sensitive to \init when trimmingEddie Hung2019-10-021-32/+63
* | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_commentsEddie Hung2019-10-084-68/+356
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| * | Missed thisEddie Hung2019-10-051-3/+4
| * | Add comment on why we have to match for clock-enable/reset muxesEddie Hung2019-10-053-3/+11
| * | Add note on pattern detectorEddie Hung2019-10-051-3/+7
| * | Add comments for xilinx_dsp_cascadeEddie Hung2019-10-041-12/+100
| * | Improve comments for xilinx_dsp_CREGEddie Hung2019-10-041-6/+7
| * | Fix commentEddie Hung2019-10-041-1/+1
| * | Restore optimisation for sigM.empty()Eddie Hung2019-10-041-1/+4
| * | Retry on fixing TODOsEddie Hung2019-10-042-13/+1
| * | Revert "Fix TODOs"Eddie Hung2019-10-042-0/+20
| * | More comments, cleanupEddie Hung2019-10-042-41/+108
| * | Fix TODOsEddie Hung2019-10-042-20/+0
| * | ConsistencyEddie Hung2019-10-041-3/+3
| * | Add comments for xilinx_dspEddie Hung2019-10-043-6/+134
* | | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarryClifford Wolf2019-10-061-0/+4
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| * | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-051-0/+4
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* | | Update README.mdClifford Wolf2019-10-051-1/+1
* | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fixMiodrag Milanović2019-10-051-0/+1
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| * | Fixes for MSVC buildMiodrag Milanovic2019-10-041-0/+1
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* / Fix xilinx_dsp for unsigned extensionsEddie Hung2019-10-041-1/+3
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* Ooops AREG and BREG to default to -1Eddie Hung2019-09-271-2/+2
* Update doc with max cascade chain of 20Eddie Hung2019-09-261-2/+4
* Do not always zero out C (e.g. during cascade breaks)Eddie Hung2019-09-262-7/+3
* Update docEddie Hung2019-09-261-1/+2
* Zero out portsEddie Hung2019-09-261-2/+2
* xilinx_dsp_cascade to also cascade AREG and BREGEddie Hung2019-09-262-454/+172
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