| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add comment on why we have to match for clock-enable/reset muxes | Eddie Hung | 2019-10-05 | 1 | -1/+4 |
| * | Add comments for xilinx_dsp_cascade | Eddie Hung | 2019-10-04 | 1 | -12/+100 |
| * | Ooops AREG and BREG to default to -1 | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| * | Do not always zero out C (e.g. during cascade breaks) | Eddie Hung | 2019-09-26 | 1 | -5/+3 |
| * | Zero out ports | Eddie Hung | 2019-09-26 | 1 | -2/+2 |
| * | xilinx_dsp_cascade to also cascade AREG and BREG | Eddie Hung | 2019-09-26 | 1 | -431/+153 |
| * | Try recursive pmgen for P cascade | Eddie Hung | 2019-09-26 | 1 | -88/+118 |
| * | Move unextend initialisation later | Eddie Hung | 2019-09-23 | 1 | -12/+9 |
| * | OPMODE is port not param | Eddie Hung | 2019-09-20 | 1 | -7/+6 |
| * | WIP for xiinx_dsp_cascadeAB | Eddie Hung | 2019-09-20 | 1 | -3/+499 |
| * | Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT | Eddie Hung | 2019-09-20 | 1 | -0/+94 |
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index : iCE40/yosys | |
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