iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth_xilinx: Use opt_dff.	Marcelina Kościelnicka	2020-07-30	1	-101/+24
\| \| \| \| \| \| \| \| \|	The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
*	xilinx: xilinx_dsp_cascade to check CREG for DSP48E1 only	Eddie Hung	2020-04-22	1	-1/+1
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*	Cleanup use of hard-coded default parameters in light of #1945	Eddie Hung	2020-04-22	1	-12/+12
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*	Minor nit fixes	Marcin Kościelnicki	2019-12-25	1	-2/+2
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*	Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too	Eddie Hung	2019-12-23	1	-8/+18
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*	Fix CEA/CEB check	Eddie Hung	2019-12-23	1	-2/+2
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*	Fix checking CE[AB] and for direct connections	Eddie Hung	2019-12-23	1	-18/+40
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*	Support unregistered cascades for A and B inputs	Eddie Hung	2019-12-23	1	-47/+74
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*	Add DSP48A* PCOUT -> PCIN cascade support	Eddie Hung	2019-12-23	1	-10/+10
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*	Add comment on why we have to match for clock-enable/reset muxes	Eddie Hung	2019-10-05	1	-1/+4
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*	Add comments for xilinx_dsp_cascade	Eddie Hung	2019-10-04	1	-12/+100
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*	Ooops AREG and BREG to default to -1	Eddie Hung	2019-09-27	1	-2/+2
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*	Do not always zero out C (e.g. during cascade breaks)	Eddie Hung	2019-09-26	1	-5/+3
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*	Zero out ports	Eddie Hung	2019-09-26	1	-2/+2
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*	xilinx_dsp_cascade to also cascade AREG and BREG	Eddie Hung	2019-09-26	1	-431/+153
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*	Try recursive pmgen for P cascade	Eddie Hung	2019-09-26	1	-88/+118
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*	Move unextend initialisation later	Eddie Hung	2019-09-23	1	-12/+9
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*	OPMODE is port not param	Eddie Hung	2019-09-20	1	-7/+6
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*	WIP for xiinx_dsp_cascadeAB	Eddie Hung	2019-09-20	1	-3/+499
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*	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	Eddie Hung	2019-09-20	1	-0/+94