aboutsummaryrefslogtreecommitdiffstats
path: root/passes/opt
Commit message (Collapse)AuthorAgeFilesLines
* opt_reduce: Add $bmux and $demux optimization patterns.Marcelina Kościelnicka2022-01-301-60/+337
|
* opt_dff: Don't mutate muxes while ModWalker is active.Marcelina Kościelnicka2022-01-281-98/+112
|
* opt_dff: fix sequence point copy paste bugAustin Seipp2022-01-041-1/+1
| | | | | | | | | | | | | | | | Newer GCCs emit the following warning for opt_dff: passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point] 560 | ff.has_clk = ff.has_ce = ff.has_clk = false; | ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Which is correct: the order of whether the read or write of has_clk occurs first is undefined since there is no sequence point between them. This is almost certainly just a typo/copy paste error and objectively wrong, so just fix it. Signed-off-by: Austin Seipp <aseipp@pobox.com>
* opt_mem_priority: Fix non-ascii char in help message.Marcelina Kościelnicka2021-12-091-1/+1
| | | | This is a fixed version of #3072.
* gowin: widelut support (#3042)Pepijn de Vos2021-11-061-2/+8
|
* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-10/+10
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-2/+12
|
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-90/+139
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* opt_merge: Remove and reinsert init when connecting nets.Marcelina Kościelnicka2021-08-221-3/+4
| | | | | | | | Mutating the SigMap by adding a new connection will throw off FfInitVals index. Work around this by removing the relevant init values from index whenever we connect nets, then re-add the new init value. Should fix #2920.
* opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-221-0/+24
| | | | | | | | | | Previously, opt_clean would reconnect all ports (including FF Q ports) to a "canonical" SigBit chosen by complex rules, but would leave the init attribute on the old wire. This change applies the same canonicalization rules to the init attributes, ensuring that init moves to wherever the Q port moved. Part of another jab at #2920.
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-142-0/+108
| | | | If all of us are wide, then none of us are!
* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-132-0/+110
|
* Add v2 memory cells.Marcelina Kościelnicka2021-08-115-9/+12
|
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-111-1/+3
|
* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-092-89/+30
| | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-081-27/+8
| | | | Partial #2920 fix.
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-23/+30
| | | | Fixes #2061.
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-282-2/+2
|
* opt_expr: Propagate constants to port connections.Marcelina Kościelnicka2021-07-271-3/+22
| | | | | | | | This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass.
* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-122/+85
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| | | | | | | | Turns out the code for div by a power of 2 is already almost capable of optimizing this to a shift-by-0 or and-with-0, which will be further folded into nothingness; let's beef it up to handle div by 1 as well. Fixes #2820.
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0817-17/+17
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* kernel/mem: Add sub_addr helpers.Marcelina Kościelnicka2021-05-261-6/+2
|
* opt_mem: Add reset/init value support.Marcelina Kościelnicka2021-05-251-0/+12
|
* opt_mem_feedback: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+15
|
* opt_mem_feedback: Add wide port support.Marcelina Kościelnicka2021-05-251-14/+24
|
* opt_mem_feedback: Rewrite feedback path finding logic.Marcelina Kościelnicka2021-05-241-115/+130
| | | | Fixes #2766.
* opt_mem_feedback: Convert to Mem helpers.Marcelina Kościelnicka2021-05-241-49/+28
|
* memory_share: Split off feedback path finding as a separate pass.Marcelina Kościelnicka2021-05-232-0/+334
| | | | | memory_share is actually three passes in a trenchcoat. Split off the one that has the least in common with the other two as a separate pass.
* opt_mem: Remove write ports with const-0 EN.Marcelina Kościelnicka2021-05-231-0/+12
| | | | Fixes #2765.
* opt_dff: Fix NOT gates wired in reverse.Marcelina Kościelnicka2021-05-041-2/+2
|
* opt_clean: Remove init attribute bits together with removed DFFs.Marcelina Kościelnicka2021-03-151-0/+4
| | | | Fixes #2546.
* opt_share: Fix X and CO signal width for shifted $alu in opt_share.Marcelina Kościelnicka2021-01-141-2/+2
| | | | | | These need to be the same length as actual Y, not visible part of Y. Fixes #2538.
* Fix use-after-free in LUT opt passStefanBruens2020-12-221-2/+4
| | | | | RTLIL::Module::remove(Cell* cell) calls `delete cell`. Any subsequent accesses of `cell` then causes undefined behavior.
* opt_mem: Use Mem helpers.Marcelina Kościelnicka2020-10-211-81/+6
|
* opt_clean: Better memory handling.Marcelina Kościelnicka2020-10-081-8/+45
| | | | | | | | Previously, `$memwr` and `$meminit` cells were always preserved (along with the memory itself). With this change, they are instead part of the main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr` cells) is only preserved iff any associated `$memrd` cell needs to be preserved.
* use the new isPublic() in a few placesN. Engelhardt2020-09-141-2/+2
|
* Merge pull request #2344 from YosysHQ/mwk/opt_share-fixesclairexen2020-08-201-223/+138
|\ | | | | opt_share: Refactor, fix some bugs.
| * opt_share: Refactor, fix some bugs.Marcelina Kościelnicka2020-08-171-223/+138
| | | | | | | | | | | | Fixes #2334. Fixes #2335. Fixes #2336.
* | Merge pull request #2337 from YosysHQ/mwk/clean-keep-wireclairexen2020-08-201-4/+9
|\ \ | | | | | | opt_clean: Fix module keep rules.
| * | opt_clean: Fix module keep rules.Marcelina Kościelnicka2020-08-091-4/+9
| |/ | | | | | | | | | | - wires with keep attribute now force a module to be kept - presence of $memwr and $meminit cells no longer forces a module to be kept
* / Remove now-redundant opt_rmdff pass.Marcelina Kościelnicka2020-08-072-712/+0
|/
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-8/+16
|
* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-312-14/+14
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* Add opt_dff pass.Marcelina Kościelnicka2020-07-302-0/+876
|
* opt_expr: Fix handling of $_XNOR_ cells with A = B.Marcelina Kościelnicka2020-07-291-1/+1
| | | | Fixes #2311.
* pmux2shift: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-15/+4
|
* wreduce: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-37/+7
|
* opt_merge: Dedup one more use of FF cell type list.Marcelina Kościelnicka2020-07-151-3/+1
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 02:13:27 +0000