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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-04 19:14:24 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-04 21:03:40 +0200 |
| commit | 5c1e6a0e201f1bb623c3fc7d2c8ee13c783c9c07 (patch) | |
| tree | 1446fa11d032acbed128ec5c8947bd071c765ee3 /passes/opt | |
| parent | d061b0e41a2023b5e72794563b94d6a9b5ab41a1 (diff) | |
| download | yosys-5c1e6a0e201f1bb623c3fc7d2c8ee13c783c9c07.tar.gz yosys-5c1e6a0e201f1bb623c3fc7d2c8ee13c783c9c07.tar.bz2 yosys-5c1e6a0e201f1bb623c3fc7d2c8ee13c783c9c07.zip | |
opt_dff: Fix NOT gates wired in reverse.
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_dff.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index a47071a30..c87ac3163 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -318,9 +318,9 @@ struct OptDffWorker if (!ff.pol_clr) { module->connect(ff.sig_q[i], ff.sig_clr[i]); } else if (ff.is_fine) { - module->addNotGate(NEW_ID, ff.sig_q[i], ff.sig_clr[i]); + module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); } else { - module->addNot(NEW_ID, ff.sig_q[i], ff.sig_clr[i]); + module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]); } log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n", i, log_id(cell), log_id(cell->type), log_id(module)); |