iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-8/+8
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-2/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-1/+1
*	Improved handling of reg init in opt_share and opt_rmdff	Clifford Wolf	2014-02-04	1	-0/+19
*	Improved opt_share for reduce cells	Clifford Wolf	2013-03-29	1	-0/+20
*	Improved opt_share for commutative standard cells	Clifford Wolf	2013-03-29	1	-1/+28
*	Added help messages for opt_* passes	Clifford Wolf	2013-03-01	1	-1/+14
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
*	initial import	Clifford Wolf	2013-01-05	1	-0/+250