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authorClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
commitcc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch)
tree2d417ab32f95d109a0d8438ae7a14acf51783c5b /passes/opt/opt_share.cc
parent665759fceee4a0db3e776b7912e976eea2ff29a3 (diff)
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Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'passes/opt/opt_share.cc')
-rw-r--r--passes/opt/opt_share.cc16
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index e3e9511fd..b3a37209b 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -66,7 +66,7 @@ struct OptShareWorker
for (auto &it : cell->parameters)
hash_string += "P " + it.first + "=" + it.second.as_string() + "\n";
- const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections;
+ const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections_;
std::map<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
@@ -135,8 +135,8 @@ struct OptShareWorker
return true;
}
- std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections;
- std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections;
+ std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections_;
+ std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections_;
for (auto &it : conn1) {
if (ct.cell_output(cell1->type, it.first))
@@ -180,8 +180,8 @@ struct OptShareWorker
}
if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
- std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->connections.at("\\Q")).to_sigbit_vector();
- std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->connections.at("\\Q")).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->connections_.at("\\Q")).to_sigbit_vector();
+ std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->connections_.at("\\Q")).to_sigbit_vector();
for (size_t i = 0; i < q1.size(); i++)
if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
lt = q1.at(i) < q2.at(i);
@@ -261,12 +261,12 @@ struct OptShareWorker
if (sharemap.count(cell) > 0) {
did_something = true;
log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
- for (auto &it : cell->connections) {
+ for (auto &it : cell->connections_) {
if (ct.cell_output(cell->type, it.first)) {
- RTLIL::SigSpec other_sig = sharemap[cell]->connections[it.first];
+ RTLIL::SigSpec other_sig = sharemap[cell]->connections_[it.first];
log(" Redirecting output %s: %s = %s\n", it.first.c_str(),
log_signal(it.second), log_signal(other_sig));
- module->connections.push_back(RTLIL::SigSig(it.second, other_sig));
+ module->connections_.push_back(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig);
}
}