aboutsummaryrefslogtreecommitdiffstats
path: root/passes/opt/opt_share.cc
Commit message (Expand)AuthorAgeFilesLines
* Bugfix for cell hash cache option in opt_share.Mingyu Gao2015-08-111-0/+2
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added opt_share -share_allClifford Wolf2015-05-311-10/+21
* Using design->selected_modules() in opt_*Clifford Wolf2015-02-031-4/+2
* bugfix in opt_shareClifford Wolf2014-12-281-0/+1
* Renamed hashmap.h to hashlib.h, some related improvementsClifford Wolf2014-12-281-1/+1
* More hashtable finetuningClifford Wolf2014-12-271-1/+1
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-261-1/+1
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-7/+11
* Added support for "keep" on modulesClifford Wolf2014-09-291-1/+1
* namespace YosysClifford Wolf2014-09-271-0/+4
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-011-1/+1
* Added design->scratchpadClifford Wolf2014-08-301-2/+2
* RIP $safe_pmuxClifford Wolf2014-08-141-1/+0
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-4/+4
* Replaced sha1 implementationClifford Wolf2014-08-011-6/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-3/+3
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-8/+8
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-8/+8
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-2/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-1/+1
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-1/+1
* Improved handling of reg init in opt_share and opt_rmdffClifford Wolf2014-02-041-0/+19
* Improved opt_share for reduce cellsClifford Wolf2013-03-291-0/+20
* Improved opt_share for commutative standard cellsClifford Wolf2013-03-291-1/+28
* Added help messages for opt_* passesClifford Wolf2013-03-011-1/+14
* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-271-1/+1
* initial importClifford Wolf2013-01-051-0/+250