iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Bugfix for cell hash cache option in opt_share.	Mingyu Gao	2015-08-11	1	-0/+2
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Added opt_share -share_all	Clifford Wolf	2015-05-31	1	-10/+21
*	Using design->selected_modules() in opt_*	Clifford Wolf	2015-02-03	1	-4/+2
*	bugfix in opt_share	Clifford Wolf	2014-12-28	1	-0/+1
*	Renamed hashmap.h to hashlib.h, some related improvements	Clifford Wolf	2014-12-28	1	-1/+1
*	More hashtable finetuning	Clifford Wolf	2014-12-27	1	-1/+1
*	Replaced std::unordered_map as implementation for Yosys::dict	Clifford Wolf	2014-12-26	1	-1/+1
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-7/+11
*	Added support for "keep" on modules	Clifford Wolf	2014-09-29	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01	1	-1/+1
*	Added design->scratchpad	Clifford Wolf	2014-08-30	1	-2/+2
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-1/+0
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-4/+4
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	1	-6/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-3/+3
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-8/+8
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-8/+8
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-2/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-1/+1
*	Improved handling of reg init in opt_share and opt_rmdff	Clifford Wolf	2014-02-04	1	-0/+19
*	Improved opt_share for reduce cells	Clifford Wolf	2013-03-29	1	-0/+20
*	Improved opt_share for commutative standard cells	Clifford Wolf	2013-03-29	1	-1/+28
*	Added help messages for opt_* passes	Clifford Wolf	2013-03-01	1	-1/+14
*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27	1	-1/+1
*	initial import	Clifford Wolf	2013-01-05	1	-0/+250