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* Added design->scratchpadClifford Wolf2014-08-301-2/+3
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-1/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-18/+18
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-26/+26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-26/+26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-2/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-7/+7
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-7/+7
* Fixed detection of init attribute in opt_rmdffClifford Wolf2014-02-041-1/+1
* Improved handling of reg init in opt_share and opt_rmdffClifford Wolf2014-02-041-7/+29
* Added constant-clock case to opt_rmdffClifford Wolf2014-02-021-0/+8
* Added support for $adff with undef data inputs to opt_rmdffClifford Wolf2014-01-171-0/+6
* Added log_abort() apiClifford Wolf2013-05-241-1/+1
* Some improvements in opt_rmdffClifford Wolf2013-05-231-2/+33
* Added help messages for opt_* passesClifford Wolf2013-03-011-1/+16
* initial importClifford Wolf2013-01-051-0/+135