iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-4/+4
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-2/+2
*	remove buffers in opt_clean	Clifford Wolf	2014-10-03	1	-0/+13
*	Added support for "keep" on modules	Clifford Wolf	2014-09-29	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-8/+12
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-2/+2
*	Added design->scratchpad	Clifford Wolf	2014-08-30	1	-4/+3
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-2/+2
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-3/+4
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-2/+1
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	1	-2/+2
*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27	1	-1/+1
*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27	1	-3/+4
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-4/+4
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-5/+5
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-6/+10
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-2/+2
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-8/+8
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-8/+8
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-2/+1
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-9/+4
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-2/+0
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-10/+7
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-14/+14
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-14/+14
*	Fixed handling of "keep" attribute on wires in opt_clean	Clifford Wolf	2014-02-16	1	-2/+2
*	Only count non-trivial attributes when findinf master signal in opt_clean	Clifford Wolf	2014-02-08	1	-2/+13
*	Improved detection of primary wire for a signal in opt_clean	Clifford Wolf	2014-02-07	1	-4/+23
*	Added $assert cell	Clifford Wolf	2014-01-19	1	-1/+1
*	Fixed keep attribute on wires in opt_clean	Clifford Wolf	2013-11-08	1	-1/+1
*	Added support for "keep" attributes on wires	Clifford Wolf	2013-11-05	1	-0/+5
*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24	1	-1/+1
*	Only prefer connected signals iff they have public names	Clifford Wolf	2013-10-17	1	-5/+6
*	Avoid re-arranging signals on register outputs	Clifford Wolf	2013-10-17	1	-3/+31
*	Fixed detection of major wires in opt_clean	Clifford Wolf	2013-10-17	1	-0/+3
*	Added iopadmap pass	Clifford Wolf	2013-10-16	1	-1/+1
*	Added "clean -purge" and ";;;" support	Clifford Wolf	2013-08-11	1	-4/+19
*	Added ";;" as shortcut for "; clean;"	Clifford Wolf	2013-08-11	1	-0/+3
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09	1	-2/+2
*	Added "clean" command (less verbose opt_clean)	Clifford Wolf	2013-08-08	1	-9/+52
*	Improved handling of private names in opt_clean and rename commands	Clifford Wolf	2013-08-07	1	-2/+2
*	Added opt_clean -purge option	Clifford Wolf	2013-07-07	1	-7/+19
*	Renamed opt_rmunused to opt_clean	Clifford Wolf	2013-06-05	1	-0/+288