aboutsummaryrefslogtreecommitdiffstats
path: root/passes/opt/opt_clean.cc
Commit message (Expand)AuthorAgeFilesLines
* Connections between inputs and inouts are driven by the inputClifford Wolf2016-04-261-0/+3
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Use alphanumerical order instead of idstring idx in opt_clean compare_signals()Clifford Wolf2016-02-021-1/+1
* Fixed opt_clean handling of inout portsClifford Wolf2015-08-161-2/+2
* Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-121-25/+57
* Merge pull request #70 from gaomy3832/bugfixClifford Wolf2015-08-121-0/+10
|\
| * Remove unused blackbox modules in opt_clean.Mingyu Gao2015-08-111-0/+10
* | Added missing ct_all setup to opt_cleanClifford Wolf2015-08-111-0/+3
|/
* Fixed trailing whitespacesClifford Wolf2015-07-021-5/+5
* preserve used $-wires with init attribute in opt_cleanClifford Wolf2015-05-221-1/+1
* Added non-std verilog assume() statementClifford Wolf2015-02-261-1/+1
* Some cleanups in "clean"Clifford Wolf2015-02-241-7/+14
* Added $meminit cell typeClifford Wolf2015-02-141-1/+1
* Fixed opt_clean performance bugClifford Wolf2015-02-041-26/+26
* Using design->selected_modules() in opt_*Clifford Wolf2015-02-031-16/+10
* Added dict/pool.sort()Clifford Wolf2015-01-241-0/+4
* Cleanups in opt_cleanClifford Wolf2014-12-291-10/+10
* dict/pool changes in opt_cleanClifford Wolf2014-12-291-5/+5
* Renamed hashmap.h to hashlib.h, some related improvementsClifford Wolf2014-12-281-1/+1
* More hashtable finetuningClifford Wolf2014-12-271-1/+1
* Replaced std::unordered_set (nodict) with Yosys::poolClifford Wolf2014-12-261-1/+1
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
* Fixed various VS warningsClifford Wolf2014-10-181-1/+1
* Some cleanups in opt_cleanClifford Wolf2014-10-161-16/+9
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-4/+4
* Added $_BUF_ cell typeClifford Wolf2014-10-031-2/+2
* remove buffers in opt_cleanClifford Wolf2014-10-031-0/+13
* Added support for "keep" on modulesClifford Wolf2014-09-291-1/+1
* namespace YosysClifford Wolf2014-09-271-8/+12
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-2/+2
* Added design->scratchpadClifford Wolf2014-08-301-4/+3
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-2/+2
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-3/+4
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-2/+1
* Added SigPool::check(bit)Clifford Wolf2014-07-271-2/+2
* Fixed bug in opt_cleanClifford Wolf2014-07-271-1/+1
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-271-3/+4
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-2/+2
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-4/+4
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-5/+5
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-6/+10
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-2/+2
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-8/+8
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-8/+8
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-2/+1
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-9/+4
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-2/+0
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-10/+7
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-1/+1
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-26 17:17:52 +0000