| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. | Marcelina Kościelnicka | 2022-06-02 | 1 | -4/+15 |
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| * | memory_dff: Add support for no_rw_check attribute. | Marcelina Kościelnicka | 2022-06-02 | 1 | -0/+10 |
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| * | FfData: some refactoring. | Marcelina Kościelnicka | 2021-10-07 | 1 | -1/+1 |
| | | | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases | ||||
| * | kernel/ff: Refactor FfData to enable FFs with async load. | Marcelina Kościelnicka | 2021-10-02 | 1 | -7/+15 |
| | | | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load | ||||
| * | memory_dff: Recognize soft transparency logic. | Marcelina Kościelnicka | 2021-08-13 | 1 | -7/+451 |
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| * | memory_dff: Recognize read ports with reset / initial value. | Marcelina Kościelnicka | 2021-08-11 | 1 | -7/+0 |
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| * | kernel/mem: Introduce transparency masks. | Marcelina Kościelnicka | 2021-08-11 | 1 | -1/+2 |
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| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
| * | Add new helper class for merging FFs into cells, use for memory_dff. | Marcelina Kościelnicka | 2021-05-23 | 1 | -237/+104 |
| | | | | | Fixes #1854. | ||||
| * | memory_dff: Use Mem helper. | Marcelina Kościelnicka | 2021-05-21 | 1 | -19/+26 |
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| * | memory_dff: Remove now-useless write port handling. | Marcelina Kościelnicka | 2021-03-08 | 1 | -71/+7 |
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| * | memory_dff: Remove code looking for $mux cells. | Marcelina Kościelnicka | 2021-03-08 | 1 | -56/+12 |
| | | | | | This job is now performed by `opt_dff`, which runs before this pass. | ||||
| * | memory_dff: Fix needlessly duplicating enable bits. | Marcelina Kościelnicka | 2020-10-22 | 1 | -0/+8 |
| | | | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409. | ||||
| * | memory_dff: Refactor to use FfInitVals. | Marcelina Kościelnicka | 2020-07-24 | 1 | -12/+5 |
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| * | memory_dff: recognize more dff cells | Marcelina Kościelnicka | 2020-07-23 | 1 | -11/+112 |
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| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -2/+2 |
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| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -46/+46 |
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| * | kernel: use more ID::* | Eddie Hung | 2020-04-02 | 1 | -8/+8 |
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| * | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
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| * | memory_dff: Fix checking of feedback mux input when more than one mux | David Shah | 2019-07-02 | 1 | -3/+5 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Fix spacing | Eddie Hung | 2019-06-25 | 1 | -4/+3 |
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| * | Move only one consumer check outside of while loop | Eddie Hung | 2019-06-25 | 1 | -6/+5 |
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| * | Walk through as many muxes as exist for rd_en | Eddie Hung | 2019-06-24 | 1 | -8/+16 |
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| * | memory_dff: Fix typo when checking init value | David Shah | 2018-12-18 | 1 | -1/+1 |
| | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Disable memory_dff for initialized FFs | Clifford Wolf | 2018-05-28 | 1 | -1/+19 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 |
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| * | Fixed some visual studio warnings | Clifford Wolf | 2016-02-13 | 1 | -1/+1 |
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| * | Bugfix in memory_dff | Clifford Wolf | 2015-10-31 | 1 | -1/+12 |
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| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -9/+43 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | Modernized memory_dff (and fixed a bug) | Clifford Wolf | 2015-06-14 | 1 | -147/+164 |
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| * | Merge clock inverters in memory_dff | Clifford Wolf | 2015-06-09 | 1 | -16/+37 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -6/+10 |
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| * | Fixed $memwr/$memrd order in memory_dff | Clifford Wolf | 2014-09-16 | 1 | -4/+6 |
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| * | Various improvements in memory_dff pass | Clifford Wolf | 2014-08-06 | 1 | -21/+22 |
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| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -19/+19 |
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| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
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| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+0 |
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| * | Using new obj iterator API in a few places | Clifford Wolf | 2014-07-27 | 1 | -15/+11 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
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| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -7/+2 |
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| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -4/+7 |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -19/+19 |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -19/+19 |
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| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -1/+0 |
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| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 1 | -8/+4 |
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| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵ | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| | | | | | created interim RTLIL::SigSpec::chunks_rw() | ||||
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -6/+6 |
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index : iCE40/yosys | |
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