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* namespace YosysClifford Wolf2014-09-271-6/+10
* Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-161-4/+6
* Various improvements in memory_dff passClifford Wolf2014-08-061-21/+22
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-19/+19
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-15/+11
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-7/+2
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+7
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-19/+19
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-19/+19
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-1/+0
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-8/+4
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-6/+6
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-6/+6
* Fixed log messages in memory_dffClifford Wolf2014-06-011-0/+2
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-28/+39
* A fix in memory_dff for write ports with static addressesClifford Wolf2013-12-011-10/+10
* Added help messages to memory_* passesClifford Wolf2013-03-011-3/+17
* initial importClifford Wolf2013-01-051-0/+200