iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-1/+0
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-8/+4
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-6/+6
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-6/+6
*	Fixed log messages in memory_dff	Clifford Wolf	2014-06-01	1	-0/+2
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-28/+39
*	A fix in memory_dff for write ports with static addresses	Clifford Wolf	2013-12-01	1	-10/+10
*	Added help messages to memory_* passes	Clifford Wolf	2013-03-01	1	-3/+17
*	initial import	Clifford Wolf	2013-01-05	1	-0/+200