iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-7/+19
*	Moved some passes to other source directories	Clifford Wolf	2014-02-08	2	-0/+351
*	Added hierarchy -purge_lib option	Clifford Wolf	2014-02-04	1	-3/+14
*	Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))	Martin Schmölzer	2014-01-14	1	-0/+1
*	Added hierarchy -libdir option	Clifford Wolf	2014-01-14	1	-4/+48
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	1	-1/+1
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	1	-60/+0
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	1	-1/+1
*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24	1	-0/+17
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-3/+3
*	Added resolution of positional arguments to hierarchy pass	Clifford Wolf	2013-11-03	1	-0/+57
*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24	1	-2/+2
*	Improved log messages generated by hierarchy pass	Clifford Wolf	2013-05-26	1	-5/+17
*	Fixed hierarchy pass for hierarchies of parametric modules	Clifford Wolf	2013-04-26	1	-0/+1
*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28	1	-2/+5
*	Collect parameters in hierarchy -generate (and do nothing with them)	Clifford Wolf	2013-03-26	1	-1/+8
*	Added hierarchy -generate command for generating skeletton modules	Clifford Wolf	2013-03-25	1	-1/+165
*	Implemented general handler for selection arguments	Clifford Wolf	2013-03-03	1	-1/+2
*	Added online help for "show" and "hierarchy" commands	Clifford Wolf	2013-02-28	1	-3/+25
*	initial import	Clifford Wolf	2013-01-05	2	-0/+197