| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Do not the 'z' modifier in format string (another win32 fix) | Clifford Wolf | 2014-10-11 | 1 | -1/+1 |
| * | Moved patmatch() to yosys.cc | Clifford Wolf | 2014-10-10 | 1 | -1/+0 |
| * | Replaced fnmatch() with patmatch() | Clifford Wolf | 2014-10-10 | 1 | -5/+4 |
| * | set "keep" on modules with $assert cells in "hierarchy" | Clifford Wolf | 2014-09-30 | 1 | -0/+30 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -11/+13 |
| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -4/+4 |
| * | Added module->ports | Clifford Wolf | 2014-08-14 | 1 | -0/+2 |
| * | More bugfixes related to new RTLIL::IdString | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -15/+15 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
| * | Allow "hierarchy -generate" for $__ cells | Clifford Wolf | 2014-07-29 | 1 | -1/+3 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -2/+2 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -30/+30 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -4/+4 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -4/+1 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -2/+2 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -5/+5 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -5/+5 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
| * | fixed cell array handling of positional arguments | Clifford Wolf | 2014-06-07 | 1 | -2/+11 |
| * | Add support for cell arrays | Clifford Wolf | 2014-06-07 | 1 | -0/+34 |
| * | Implemented read_verilog -defer | Clifford Wolf | 2014-02-13 | 1 | -7/+19 |
| * | Added hierarchy -purge_lib option | Clifford Wolf | 2014-02-04 | 1 | -3/+14 |
| * | Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3)) | Martin Schmölzer | 2014-01-14 | 1 | -0/+1 |
| * | Added hierarchy -libdir option | Clifford Wolf | 2014-01-14 | 1 | -4/+48 |
| * | Replaced signed_parameters API with CONST_FLAG_SIGNED | Clifford Wolf | 2013-12-04 | 1 | -1/+1 |
| * | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 | 1 | -60/+0 |
| * | Implemented correct handling of signed module parameters | Clifford Wolf | 2013-11-24 | 1 | -1/+1 |
| * | Added "top" attribute to mark top module in hierarchy | Clifford Wolf | 2013-11-24 | 1 | -0/+17 |
| * | Renamed "placeholder" to "blackbox" | Clifford Wolf | 2013-11-22 | 1 | -3/+3 |
| * | Added resolution of positional arguments to hierarchy pass | Clifford Wolf | 2013-11-03 | 1 | -0/+57 |
| * | Fixed handling of boolean attributes (passes) | Clifford Wolf | 2013-10-24 | 1 | -2/+2 |
| * | Improved log messages generated by hierarchy pass | Clifford Wolf | 2013-05-26 | 1 | -5/+17 |
| * | Fixed hierarchy pass for hierarchies of parametric modules | Clifford Wolf | 2013-04-26 | 1 | -0/+1 |
| * | Implemented proper handling of stub placeholder modules | Clifford Wolf | 2013-03-28 | 1 | -2/+5 |
| * | Collect parameters in hierarchy -generate (and do nothing with them) | Clifford Wolf | 2013-03-26 | 1 | -1/+8 |
| * | Added hierarchy -generate command for generating skeletton modules | Clifford Wolf | 2013-03-25 | 1 | -1/+165 |
| * | Implemented general handler for selection arguments | Clifford Wolf | 2013-03-03 | 1 | -1/+2 |
| * | Added online help for "show" and "hierarchy" commands | Clifford Wolf | 2013-02-28 | 1 | -3/+25 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+194 |
