iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06	1	-3/+3
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-1/+1
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09	1	-24/+27
*	Sort ctrl signals in fsm_extract	Clifford Wolf	2013-08-08	1	-0/+3
*	Renamed opt_rmunused to opt_clean	Clifford Wolf	2013-06-05	1	-1/+1
*	Added [[CITE]] tags to abc and fsm_extract passes	Clifford Wolf	2013-03-15	1	-1/+6
*	Added help messages for fsm_* passes	Clifford Wolf	2013-03-01	1	-2/+22
*	Copy attributes from state signal to fsm cell	Clifford Wolf	2013-01-05	1	-0/+1
*	initial import	Clifford Wolf	2013-01-05	1	-0/+359